Associative memory device

A technology of memory and clock devices, applied in the field of memory engines, which can solve the problems of increased processing time, reduced utility, and lack of flexibility in search architectures

Inactive Publication Date: 2007-11-21
ALLSEARCH SEMI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although these known associative systems are useful to some extent, they still suffer from the inflexibility of the search architecture, so their utility is correspondingly reduced, while their processing time is increased.

Method used

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  • Associative memory device
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Embodiment Construction

[0049] A CM is a physical backing for strings of words each drawing a value from a finite memory symbol set, with each word incremented by "setting" an additional bit, thereby causing the word to have one of two states: marked or unmarked . The term "memory symbol" is interpreted herein to mean a fixed-length set of consecutive bits, the length of which is application-dependent and for which no a priori value is set.

[0050] The structure of the present invention allows all CM commands to be executed in one clock cycle, with a latency that is approximately twice that typically encountered in current cache memory technology. The structure described in this paper belongs to a single set-up circuit, and it can also be replicated in a more sophisticated circuit. Figure 1 illustrates the general architecture of memory engine 205, and its operational relationship with external controller 255 and synchronous clock circuit 256, according to one embodiment of the invention. It will ...

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Abstract

An associative memory support for a data processing system includes an associative memory device containing n-cells. A controller is provided for issuing an instruction to the associative memory device. A clock device outputs a synchronizing clock signal that includes a predetermined number of clock cycles per second, the clock device outputting the synchronizing clock signal to the associative memory device and the controller. The controller globally communicates the instruction to all of the n-cells simultaneously, within one of the clock cycles and the instruction is applied equally to each of the n-cells.

Description

[0001] Cross References to Related Applications [0002] This application is a continuation-in-part and claims the benefit of priority from: Allowed U.S. Patent Application Serial No. 09 / 928,151, filed August 10, 2001, now U.S. Patent No. 6,760,821, entitled "For Data Inspection and A MEMORY ENGINE FOR THE INSPECTION ANDMANIPULATION OF DATA, and including U.S. Patent Application Serial No. 10 / 728,234, filed December 4, 2003, entitled "Data Processing System for a Cartesian Controller" (DATA PROCESSING SYSTEM FOR A CARTESIAN CONTROLLER) and the substantive subject matter of U.S. Patent Application Serial No. 10 / 727,811, filed December 4, 2003, entitled "CELLULAR ENGINEFOR A DATA PROCESSING SYSTEM," by Both are incorporated herein by reference in their entirety. technical field [0003] The present invention relates generally to associative memory support for data processing, and more particularly to a memory engine utilizing improved associative technology to provide faster da...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/00G11C15/00
CPCG11C15/00G06F12/00
Inventor G·斯蒂芬D·蒂鲍特D·托梅斯库
Owner ALLSEARCH SEMI
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