Chip stacking structure forming method

Abstract

The invention relates to a chip packaging structure and a forming method thereof. The packaging structure comprises a chip, a packaging body, a first patterned protection layer, a metal layer, a second patterned protection layer, a plurality of patterned UBM layers and a plurality of conductive assemblies, wherein a plurality of soldering pads and adhesion layers are respectively arranged on an active surface and a back surface of the chip; the packaging body is annularly covered on four surfaces of the chip so as to expose the soldering pads of the chip out and is provided with a plurality of through holes; the first patterned protection layer is formed on the partial surface of the packaging body and the active surface of the partial chip and exposes the soldering pads and the through holes out; the metal layer is covered on the partial surface of the first patterned protection layer, and is electrically connected with the soldering pads and filled in the through holes; the second patterned protection layer is covered on the first patterned protection layer and a part of metal layer and exposes the partial surface of the metal layer out; the patterned UBM layers are formed on the partial surface of the exposed metal layer and the partial surface of the second patterned protection layer and are electrically connected with the metal layer; and the conductive assemblies are formed on the patterned UBM layers and electrically connected with the metal layer through the patterned UBM layers.

Description

technical field [0001] The present invention relates to a semiconductor packaging structure and method, in particular to a chip stacking structure and packaging method. Background technique [0002] Semiconductor technology has developed quite rapidly, so the miniaturized semiconductor chip (Dice) must have diversified functional requirements, so that the semiconductor chip must be configured with more input / output pads (I / O pads) in a small area. O pads), so that the density of metal pins (pins) is also rapidly increased. Therefore, the early lead frame packaging technology is no longer suitable for high-density metal pins; therefore, a ball array (Ball Grid Array: BGA) packaging technology has been developed. The ball array package has the advantage of higher density than the lead frame package. In addition, its solder balls are less prone to damage and deformation. [0003] With the popularity of 3C products, such as: mobile phone (Cell Phone), personal digital assistan...

AI Technical Summary

Problems solved by technology

This thinned chip is reconfigured on another substrate, and then multiple chips are formed into a package by injection molding; because the chip is very thin, the package is also very thin, so when the package is detached After the substrate, the stress of the package itself will cause the package to warp, increasing the difficulty of the subsequent cutting process

[0006] In addition, after the wafer is diced, when it is reconfigured on another carrier, because the size of the new carrier is larger than the original size, it will not be aligned in the subsequent ball planting process, and the reliability of the package structure will be reduced.

[0007] In addition, during the entire packaging process, there will also be a problem that the manufacturing equipment will generate excessive local pressure on the chip during ball planting, which may damage the chip; at the same time, it may also be caused by the material of the ball planting. The resistance value between the pads becomes larger, which affects the performance of the chip and other issues

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