Memory test system

Abstract

The invention provides a memory test system, which can solve a test problem caused by a high-speed memory interface and a synchronous dynamic random access memory (SDRAM). Each hardware mode in the memory test system can be set independently so as to combine into diversity of test samples, which can execute programmable test of difficult loads, practical example test and write-in feedback test. Simultaneously the write-in feedback test of the memory test system can independently test a memory controller, so that the system can test a memory controller which is embedded into an integrated circuit without communicating with an entity SDRAM. In addition, in a validation stage of the integrated circuit, the technology of the invention can be used for analyzing and distinguishing whether a problem point is in or out of the integrated circuit, and testing a write-in command and a read-out command.

Description

technical field

[0001] The invention relates to a dynamic random access memory, in particular to a memory testing system. Background technique

[0002] In the past few years, due to the progress of the semiconductor manufacturing process, the cell of the synchronous dynamic random access memory can reach 4 Giga bits or more. And the data transmission capacity of each data pin can also reach 1600Mbps / pin or higher. In the synchronous dynamic random access memory (SDRAM) system, the density and speed of the synchronous dynamic random access memory are rapidly increased and increased, and the traces of the electronic transmission signal on the printed circuit board are connected to the pins of the integrated circuit The required speed also increases rapidly. Therefore, whether it is a personal computer system or a consumer electronic product, the Synchronous Dynamic Random Access Memory has become the most important storage device and plays the role of the main memory at the ...

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