Asynchronous counter circuit and realizing method thereof

A counter and circuit technology, which is applied in the field of asynchronous counter circuits, can solve problems such as circuit instability, reset signal glitches, and flip-flops not being reset, so as to avoid reset instability, remove glitches, and improve reliability and stability. Effect

CN102111147AActive Publication Date: 2011-06-29HUADA SEMICON CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2011-06-29

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Abstract

The invention discloses an asynchronous counter circuit and a realizing method thereof. The asynchronous counter circuit comprises a trigger cascade circuit, a numerical value comparison circuit and a counter reset signal processing circuit, wherein the trigger cascade circuit realizes a basic counting function; when a count value reaches a design value, the numerical value comparison circuit generates a mark signal; after the mark signal passes through the counter reset signal processing circuit, a stable and effective reset signal can be generated for resetting a trigger in the trigger cascade circuit; therefore, a set counting function is realized. By using the circuit given by the invention, the phenomenon that the reset of the asynchronous counter circuit is unreliable is solved, andthe stability and the reliability of the circuit are improved.
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Description

technical field

[0001] The invention relates to an asynchronous counter circuit and method. It can be used in the design of integrated circuits that need to realize the counting function and have low power consumption requirements. Background technique

[0002] A counter circuit is one of the most basic circuits often used in integrated circuit design. According to the different clock pulse input methods, it can be divided into synchronous counters and asynchronous counters. All flip-flops in the synchronous counter circuit work on the count clock, and the control logic is relatively complex, so the power consumption is relatively large. In the asynchronous counter circuit, usually only the first-stage flip-flop works on the counting clock, and the power consumption is relatively small.

[0003] In a common asynchronous counter circuit structure, when the count value reaches the design value, the reset signal generated by the decoding circuit will reset the count flip-flo...

Examples

Embodiment Construction

[0017] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0018] figure 1 It is a circuit structure diagram of a 12-ary asynchronous up-counter designed according to the circuit and method disclosed in the present invention.

[0019] In this specific implementation example, the flip-flop cascade circuit is composed of four falling-edge triggered D flip-flops DFF1-DFF4, and the D terminals of each flip-flop are respectively connected to their own inverting output terminals Q. The clock terminal of the first-stage flip-flop DFF1 is connected to the input clock, and the clock terminal of the subsequent-stage flip-flop is connected to the data output terminal of the previous-stage flip-flop. When the falling edge of the input clock arrives, DFF1 flips; when the Q terminal of the previous flip-flop flips from 1 to 0, the input of the next flip-flop flips.

[0020] The value comparison circuit is compose...