9 results about "Cascade circuits" patented technology

This disclosure is directed to digital front-end circuitry of a memory device having widened operating frequency bandwidth. The digital front-end circuitry may include a receiver including a variable gain amplifier (VGA) and a continuous time linear equalizer (CTLE) integrated on three cascaded circuit stages. A first stage of the three cascaded circuit stages may include a first portion of the VGA and a first portion of the CTLE, a second stage may include a remaining portion of the VGA, and a third stage may include a remaining portion of the CTLE. Having three cascaded circuit stages (e.g., including the remaining portion of the CTLE) as opposed to two cascaded stages may widen the operating frequency bandwidth of the receiver. The third stage may be programmable to be activated or deactivated.

Provided A gate drive circuit includes: a first frame start signal line and a cascade circuit. The first frame start signal line is connected to a first input terminal of the cascade circuit, configured to transmit a first frame start signal to the cascade circuit in a first display stage. The cascade circuit includes shift registers. Each shift register is connected to a clock signal line. An output terminal of each shift register is connected to a writing module in a pixel drive circuit. The cascade circuit is configured to output first scanning signals stage by stage according to the first frame start signal and a clock signal from the clock signal line. The effective level of the first frame start signal in one period overlaps with a plurality of pulse signals of the clock signal. The first scanning signal includes a plurality of scanning pulse signals in one period.

The application relates to the technical field of high-speed electronic design automation simulation, and further relates to a via simulation method and system, a computer device and a storage medium. The method comprises the following steps: decomposing a multilayer via structure into multiple units, each unit comprising a cavity formed by a pair of plates and at least one via segment passing through the cavity; calculating an inter-plate impedance matrix of the cavity in each unit according to a finite element algorithm; calculating a coupling capacitance between the cavity and the via segment in each unit according to an analytical method; constructing multiple pi-type coupling circuit models according to the inter-plate impedance matrix and the coupling capacitance corresponding to each unit; cascading the pi-type coupling circuit models of each layer to obtain a multilayer via cascaded circuit model; and calculating scattering parameters according to the multilayer via cascaded circuit model. The method accurately and efficiently simulates a multilayer structure comprising vias, traces and an actual power ground plane, and realizes collaborative design of signal integrity and power integrity.

The application relates to the field of advanced packaging technology of integrated circuits, and particularly relates to a manufacturing method of a standard power unit structure for embedded packaging. The method comprises the following steps: obtaining design parameters of all standard power units, performing patterned electroplating at one end of a copper plate to form a chip accommodating cavity and a positioning mark target, opening a blind groove in the copper plate to form an insulating area and a cutting area, dividing the copper plate into multiple copper base tables, retaining a layered structure of the copper plate as a connecting layer, mounting a chip to the chip accommodating cavity, performing whole-plate plastic packaging, windowing, laser drilling and metallization, forming interconnection vias and top external vias, manufacturing a rewiring layer, forming a half-bridge circuit, a full-bridge circuit, a cascade circuit, a multi-core series circuit, a multi-core parallel circuit or a single-core circuit, and removing the connecting layer to cut to obtain a standard power unit product. The application can batch-manufacture standard power units with high-efficiency heat dissipation function and different circuit structures including a multi-core series structure.

A cascode circuit is formed using a high voltage transistor in series with a low voltage transistor. A clamp switch device is used to discharge the gate of the high voltage transistor when the cascode is off. Rate limiting devices may be used control turn on and turn off characteristics of the cascode. Rate limiting devices may be include resistors and / or transistors. The high voltage transistor may be a normally on silicon carbide JFET, for example, and the low voltage transistor may be a silicon MOSFET.

A display device (200) and a display method are disclosed. The display device (200) includes a display panel (210) and a first driving circuit (220) electrically connected to the display panel (210), a first power supply line (VGH1), and a second power supply line (VGH2). The first driving circuit (220) includes M shift registers. The gating circuit of the m-th shift register is electrically connected to the output terminal of the cascaded circuit of the (m-1)-th stage shift register. The first power supply line (VGH1) is electrically connected to the cascaded circuit of the odd-numbered stage shift registers among the M shift registers, and the second power supply line (VGH2) is electrically connected to the cascaded circuit of the even-numbered stage shift registers among the M shift registers. The cascaded circuit of the M shift registers outputs M cascaded signals based on the first power supply voltage (VGH1) and the second power supply voltage (VGH2). Under the control of the cascaded signals output by the (m-1)-th stage shift register, the gating circuit of the m-th shift register outputs a first scan signal based on the gating signal. The cascaded signal controls the gating signal to be written into the gating circuit, and the gating signal controls the level of the first scan signal.

This disclosure relates to amplifier circuits, low-noise amplifiers, apparatuses, and methods for performing amplification. Embodiments provide amplifier circuits, apparatuses for performing amplification, low-noise amplifiers, radio receivers, mobile terminals, base stations, and methods for performing amplification. An amplifier circuit 10 for amplifying radio signals includes components configured to amplify an input signal V. in (t) A first amplification stage 12 is used to amplify the intermediate signal to obtain an intermediate signal. Circuit 10 also includes a first output signal V configured to amplify the intermediate signal to obtain a first output signal V. outn The cascaded circuit 14 of (t) is also included. Circuit 10 further includes amplification of the intermediate signal to obtain a second output signal V. outp The second amplification stage of (t) is 16.

The application provides a double-line cascaded LED driving circuit and a communication method thereof, which adopts two lines, namely a clock line and a data line, and realizes data communication and connection between LED drivers through a two-line input and two-line output communication mode; meanwhile, the LED driver obtains a forwarding identifier in input data through a data cascaded circuit arranged in the LED driver, and takes the clock signal and the data corresponding to the forwarding identifier as input driving data of a next-stage LED driver based on the forwarding identifier, so that the LED driver of the whole driving unit only needs to drive one LED driver, high-speed data transmission can be realized, and the wiring mode and hardware wiring difficulty between a controller and the LED driver and between the LED drivers are simplified.

A cascade circuit including a preceding-stage buck-boost circuit and a post-stage isolation switch power supply circuit is provided. One end of the switch transistor Q1 serves as a positive input of the buck-boost circuit, and the other end is connected to one end of the switch transistor Q2 and one end of the inductor L. The other end of the inductor L, one end of the switch transistor Q4, and one end of the capacitor C1 are connected to serve as a positive output of the buck-boost circuit. The other end of the capacitor C1 is connected to one end of the switch transistor Q3. The other end of the switch transistor Q2, the other end of the switch transistor Q4, and the other end of the switch transistor Q3 are connected to serve as an input power supply ground of the buck-boost circuit.