239 results about "Cascade circuits" patented technology

The invention discloses a switching power supply for an AC / DC-DC self-adaptive instrument within an ultra-wide voltage input range. The switching power supply comprises an input protective circuit, an EMI filter circuit, a power frequency rectification and filter circuit, a high frequency rectification and filter circuit, a boosting conversion circuit, a flyback conversion circuit, a first voltage sampling circuit, a first current sampling circuit, a second voltage sampling circuit, a second current sampling circuit, a first PWM circuit, a second PWM circuit, an auxiliary power supply circuit, a power switching circuit, a voltage detection and comparison control circuit and an optocoupler isolation feedback circuit. A two-stage type cascade circuit is formed by the boosting conversion circuit and the flyback conversion circuit, and the automatic instrument can automatically adapt to power supply of an 85-265V alternating-current power supply and an 18-100V direct-current power supply.

A device for non-contact transmission of electrical signals or energy between two parts mobile relative to each other comprising electromagnetic near-field coupler elements on the two parts, wherein the coupler elements on at least one part form a cascade circuit terminated in a manner substantially free from reflection, and each coupler element is an independent resonance system having a resonance frequency higher than a highest frequency of wide-band signals to be transmitted. An alternatively structured device in which each coupler element on one part includes an element that resonates independently and has a resonance frequency approximately equal to the frequency of signals or energy to be transmitted including developments in which the coupler elements operate on differential signals, or analyzer means determine the spacing between the two parts, or at least one part comprises symmetrical lines for supplying differential energy signals to two coupler elements.

An improved refrigerant system incorporates at least two circuits arranged in a cascaded relationship. Preferably, the upper circuit utilizes a hydrocarbon refrigerant and preferably the lower circuit utilizes CO2 refrigerant. Preferably, the CO2 circuit mainly operates in a subcritical region. To improve the efficiency and capacity control of the cascaded refrigerant system, at least one of the circuits is equipped with performance enhancement features such as, for example, an economized function provided by a flash tank or economizer heat exchanger. Additional enhancement features can also include a liquid-suction heat exchanger and bypass function.

An anti-serial cascade circuit including two silicon carbide JFETs and two silicon MOSFETs is known. Disclosed is a combination of a JFET, a smart power MOSFET SPM and a thyristor with an associated trigger circuit, which is connected in parallel to the SPM. According to an embodiment of the invention, a logic circuit co-ordinates the functional sequence.

The invention relates to a capacitive micro-accelerometer which adopts the design of a bulk-silicon processed micro-mechanical structure and the design of an integrated circuit, which pertains to the field of MEMS micro-inertial instruments. The capacitive micro-accelerometer adopts two chips of a micro-mechanical sensor and a signal processing circuit for respective integration, the capacitive micro-accelerometer is carried out by the overall packaging and finally realizes an internal structure of the packaged system; the micro-mechanical sensor of the invention adopts a full-differential micro-mechanical structure sensitive element to be matched with a follow-up circuit; the signal processing circuit comprises a full-differential switched capacitor charge amplifier front-end circuit module with adjustable gain, a back-end cascade circuit module which is composed of a first-order switched capacitor low-pass filter and an instrument amplifier and an auxiliary circuit module which is composed of a reference voltage and bias current generating circuit, a self-test circuit and a clock generating circuit. The two-chip proposal of the system of the invention carries out the respective integration and overall packaging, thus simplifying the complexity of the system, reducing the processing cost and the difficulty and improving the performance and the yield.

The converter includes six pieces of three phase bridge arm including full controlled main switch with diode connected in inverted parallel, input inductance connected between power source and middle point of each phase bridge arm, and output capacitance connected to output end of three phase bridge arm. Characters are that capacitance is connected to six main switches respectively. Resonant inductance is connected to DC bus of three-phase bridge arm and output capacitance. Cascaded circuit of auxiliary switch and clamping capacitance is cross-connected on two ends of resonant inductance. Two ends of the auxiliary switch are connected to diode in inverted parallel as well as connected to capacitance. Features of the converter are simple structure, restraining backward recovery of diode connected in inverted parallel, realization of soft switch and high efficiency of circuit.

An arrangement with a control circuit for controlling a numerical value for patient respiration as well as to a process for controlling the numerical value. The numerical value is controlled on the basis of an evaluation of the EEG (electroencephalogram) of the patient (1) by an EEG sensor (2), e.g., by determining the so-called BIS (bispectral index). A control of the inspiratory gaseous anesthetic concentrations is cascaded to the control of the EEG value in the manner of a cascade circuit. This has the advantage that a metering device (6) belonging to the arrangement meters a gaseous anesthetic mixture directly according to the patient's needs. As an alternative, the control of the numerical value is performed on the basis of an evaluation of the expiratory gaseous anesthetic concentrations resolved for individual breaths at the Y-piece (19) of the respiration circuit (12) by a gaseous anesthetic sensor (8a), preferably an infrared optical gas sensor.

A power amplifier comprises a power amplification stage and an impedance transformation stage. The power amplification stage is connected with the impedance transformation stage in series. A differential cascade circuit structure is adopted in the power amplification stage, and the impedance transformation stage is formed by connecting a three-level parallel resonance network, a fundamental wave resonance network and an L-type impedance transformation network in series. The power amplifier has a linear configurable mode and a non-linear configurable mode, the working frequency range covers 0.1GHz to 1.5 GHz and optimization of linearity and efficiency can be realized through flexible configuration under different scenes.

The invention discloses a high-efficiency wideband power amplifier with a band-pass filter response function. The high-efficiency wideband power amplifier comprises a DC biasing circuit, a power amplification transistor, an input match circuit and an output match circuit. A microstrip line band-pass filter with different port impedances and a section of tuning microstrip line are designed to be used as the output match circuit of the power amplifier, the function of the filtering is achieved, meanwhile, the circuits are made to have the band-pass filter response characteristic, and two transmission zeros are generated on the edge of a passband. Compared with a traditional cascade circuit of a power amplifier and a filter, due to the fact that the microstrip line band-pass filter is used as the output match circuit, the entire circuit is small in size, small in loss and wide in working band, and high edge selectivity is achieved due to the two transmission zeros. The high-efficiency wideband power amplifier with the high-pass filter response function is achieved, and testing result validation is provided.

The present invention discloses an LED (Light Emitting Diode) module, which comprises: a plurality of LED lamps, baseplates, heat-conduction blocks, heat-conduction elements, and fixing elements. The LED lamp has an electrode plate on one side and an LED on the other side. One face of the electrode plate has two electrodes respectively arranged in two edges. A protection ring annularly surrounds the LED. The baseplate is a printed circuit board having a plurality of through-holes and cascade circuits on one side. The heat-conduction block is a metal block having an appropriate thickness and a high thermal conductivity and is attached to one side of the electrode plate to dissipate the heat generated by the LED lamps. The heat-conduction block has a plurality of fixing holes. The fixing elements are fastened into the fixing holes to join together the heat-conduction block and the baseplate. The heat-conduction element is a heat-conduction body attached to the other side of the heat-conduction block.

Y-word Search schemes under preferred hierarchical broken-GBL and broken-LBL NAND-CAM arrays with 1) one CSL line shared by two NAND blocks as a match line or 2) one LBLps line shared in each LG of H Blocks as a match line. The NAND-CAM includes three types of sense-amplifiers for Y-word search operations, including 1) an Analog SA with 3-Bias cascade circuit for LG-based LBLps match line, 2) a Digital-like SA circuit for Block-based CSL match line, and 3) an existing DR-SA along with decoders for Y-direction-CSL match line. One or more embodiments of the Y-word search operations are provided for finding one matched paired-block, then one matched block, and one matched Y-word string associated with a LBL using sequential On / Off technique without extra overhead.

A battery controller 10 outputs a voltage sampling and holding command signal to an integrated circuit CCn located at an upstream end of cascade connection of integrated circuits CC1-CCn such that integrated circuits CC1-CCn sample and hold output voltages of unit cells 1 grouped into battery modules M1-Mn. The battery controller 10, after confirming that the voltage sampling and holding command signal has been transmitted to an integrated circuit CC1 located at a downstream end of the cascade connection, outputs a transmission command signal to the integrated circuit CCn at the upstream end of the cascade circuit to transmit output voltages of the unit cells 1 held in the integrated circuits CC1-CCn to the battery controller 10. As a result, a time lag in the detection timings of output voltages of the unit cells 1 of the battery modules M1-Mn can be decreased.

The invention discloses a shift register, a gate drive circuit, a display device and a gate driving method. The shift register comprises: a display pre-charge reset circuit, a sensing cascade circuit,a sensing pre-charge reset circuit, a reverse circuit and an output circuit. The sensing cascade circuit, the display pre-charge reset circuit, and the sensing pre-charge reset circuit are connectedwith the same reverse circuit and the same output circuit. The output circuit is connected with a plurality of signal output ends. The output circuit comprises a plurality of output sub-circuits in one-to-one correspondence with the signal output ends, and the output sub-circuits are used for writing driving clock signals provided by the driving clock signal ends into the corresponding signal output ends in response to voltage control of pull-up nodes in an effective level state in a display output stage and a sensing output stage. According to the technical scheme, the number of TFTs needingto be set can be effectively reduced while double-pulse driving signals are output.

The invention provides a linear regulator with a soft start control circuit. The linear regulator comprises an operational amplifier and an output cascade circuit, wherein the operational amplifier compares a voltage distributing signal with a reference voltage of an output node of the output cascade circuit and outputs a control signal to control the output cascade circuit. When the linear regulator is in a non-start stage, the output cascade circuit outputs constant voltages. The linear regulator is characterized by further comprising the soft start control circuit and a first power drive tube, wherein the size of the first power drive tube is smaller than that of a power drive tube in the output cascade circuit, the soft start control circuit detects whether the linear regulator is in the start stage, when the linear regulator is in the start stage, the first power drive tube is started so that the linear regulator can charge a load with currents flowing through the first power drive tube, and when the linear regulator is in the non-start stage, the power drive tube in the output cascade circuit charges the load.

A converter, for use in high voltage direct and alternating current power transmission comprises a primary charge transfer converter. The charge transfer converter includes first and second primary terminals for connection to one or more electrical networks. The primary charge transfer converter also includes a plurality of charge transfer elements and a plurality of primary switching elements which are connected in a cascade circuit between the first and second primary terminals. Each charge transfer element includes at least one resonant circuit. The primary switching elements are operable to selectively cause charging and discharging of each resonant circuit to transfer charge between the charge transfer elements and thereby create a voltage difference between the first and second primary terminals.

A cascode circuit arrangement has a low voltage MOSFET and a depletion mode power device mounted on a substrate (for example a ceramic substrate), which can then be placed in a semiconductor package. This enables inductances to be reduced, and can enable a three terminal packages to be used if desired.

The invention discloses an energy storage capacitor-based cascaded inverter circuit. The energy storage capacitor-based cascaded inverter circuit consists of an asymmetrical three-level circuit and an H bridge circuit, which are cascaded, wherein the voltage output points of the asymmetrical three-level and the H bridge circuit are modulated through a switching device, and then are connected. The energy storage capacitor-based cascaded inverter circuit is characterized in that the asymmetrical three-level circuit is connected with a direct current power supply; the H bridge circuit is connected with an energy storage capacitor; and the output of the inverter circuit is the superposition of the output of the two cascaded circuits, and multi-level output can be realized by different modulation methods. Therefore, in a certain operating mode, a flying capacitor can transfer a part of electric energy of the direct current power supply into the energy storage capacitor for storage; and when a load is in a reactive state, electric energy absorbed by the direct current power supply is partially or totally transferred into the energy storage capacitor for storage.

There is disclosed an impedance conversion circuit called a regulated cascode circuit in which a parasitic capacity deteriorating frequency characteristics is reduced during operation up to about several hundreds of megahertz or higher frequencies. In the impedance conversion circuit comprising two regulated cascode circuits in which active elements and reverse amplifiers are interconnected with a feedback applied thereto, a capacity element is disposed between a control end of one active element and an output end of the other active element.

The invention relates to a power electronic electric energy conversion circuit and discloses a cascaded resonance DC-DC conversion circuit combined with an inductor and a capacitor. The front and rear cascaded circuits together utilize an inductor and a capacitor, namely the filter inductor contained in the PWM DC-DC circuit is simultaneously regarded as the input decoupling inductor of the rear cascaded DCX circuit while the resonance capacitor of the DCX circuit is simultaneously regarded as the output capacitor of the PMW DC-DC output capacitor; the switching frequency of the PWM DC-DC circuit synchronizes with that of the DCX circuit. In the conversion circuit, the front and rear cascaded inductors and capacitors are compound to promote power density; the DC-DC output voltage can be flexibly adjusted by the two-stage cascaded topological structure; wastage of the power switching tube switch is reduced through the parallel resonance technology of the soft switch; the energy conversion efficiency is promoted by collecting energy from the parasitic inductor or the capacitor; the energy consumption of the circuit is reduced and the energy is also saved; heat energy of the power switch apparatus is also decreased to improve the operation steadiness of the circuit and the service life of the apparatus and the circuit.

The invention provides a luminescence control circuit which is taken as a shift register unit circuit. The circuit comprises a first clock signal input end, a second clock signal input end, a third clock signal input end, a signal input end, a luminescence control signal output end, a constant high level voltage signal end and a constant low level voltage signal end, wherein an input control unit, a first pull-down unit, a second pull-down unit, a first pull-up unit and a second pull-up unit are connected between the signal input end and the luminescence control signal output end. The invention further provides a shift register, grid control nodes of ninth and tenth film transistors of an output level TFT have stable and controllable work voltages at each work stage, the ninth and tenth film transistors realize conduction by turns, and the simultaneous turn-off situation does not occur. According to the circuit, circuit output signal waveforms are stable, grid reliability is high, after simulation verification, output signal waveforms of each level of cascade circuits are stable.

A semiconductor device includes at least one reference cell (6), a cascode circuit (8) that has at least two current mirror circuits (30, 33 and 30, 34) and outputs voltages dependent on a current flowing through the at least one reference cell (6) to at least two output paths (55, 56), and a switch (20) that selectively connects the at least two output paths (55, 56) to a given output terminal (27).

The invention discloses a variable gain low-noise driving amplifier. The amplifier has a fully differential cascode structure, wherein a common gate consists of three side-by-side silicon germanide bipolar transistors; the central silicon germanide bipolar transistor adopts parallel capacitive feedback, a reasonable input / output matching circuit is adopted, a high variable gain is provided for a circuit, and the noise coefficient is reduced; a cascade circuit provides a high variable gain and increases the reverse isolation of the circuit at the same time; and a common source amplifying circuit further improves the gain of the circuit. By controlling the selection of an external bias, the variable gain with a 3dB step length is obtained. The variable gain low-noise driving amplifier has the characteristics of high variable gain, low noise and low power consumption.

The present invention relates to audio signal processing such as equalisation and spatial enhancement functions. The present invention provides an audio signal processing circuit arrangement for two audio channels, and which combines spatial enhancement or acoustic mixing (crosstalk) cancelling with graphic equalisation functions. This is achieved with a circuit structure having a reduced filter count compared with known cascaded circuits dedicated to each function. The circuit structure processes the sum and difference signals through separate filters and then recombines them to recover the separate channels (adding and subtracting respectively).

D trigger is composed of driving and triggering two parts of cascaded circuits. The driving circuit includes transmission gate, timeclock controlled inverting circuit and an inverter. Triggering circuit is a difference structure controlled by the timeclock controlled inverting circuits. On / off of transmission gate is controlled by timeclock singnal; when signal is in high, transmission gate is off; and when signal is in low, transmission gate is on. In on state of the transmission gate, input signal in high level is sent to trigger; when next timeclock signal in high level comes, transmission gate is turned to off; and timeclock controlled inverting circuit is turned to on to hold electrical level, and meanwhile trigger is flipped. Advantages are: simple circuit structure, few number of transistor, small area, about 40úÑ less than power consumption of traditional trigger, and about 20úÑ less than delay time. Moreover, difference input in second stage enhances performance for antinoise.

The invention discloses a driving circuit for a display panel. The display panel comprises a plurality of display areas. The driving circuit comprises a time sequence controller, a plurality of source drives and a plurality of gamma voltage generation circuits, wherein the time sequence controller is used for providing different time sequence control signals and display data signals to a plurality of display areas; each source drive corresponds to one corresponding display area in the plurality of the display areas, and is used for providing gray scale voltage corresponding to the display data signals to corresponding display areas on the basis of the time sequence control signals; the plurality of the gamma voltage generation circuits are respectively arranged on corresponding source drives of the plurality of the source drive and form a cascading circuit, and are used for providing a plurality types of gamma voltage to corresponding source drive in a cascading mode; and the plurality types of the gamma voltage are used for generating reference voltage of the gray scale voltage for corresponding source drives. By adopting the driving circuit, problems such as gray scale unbalance caused by a plurality of driving circuits in a large-size display panel can be relieved, alleviated or eliminated.

A look-up table cascade circuit having N look-up tables connected in cascade for implementing a desired logic function, comprising: N memory cell arrays for storing data of the look-up table in memory cells; N input select circuits for selecting a word line and bit lines to specify memory cells based on an input variable to the look-up table; N output circuits for selectively coupling data in the memory cells selected by the input select circuit to an input / output path and for outputting the data as an output variable of the look-up table; and N−1 connection circuits arranged between each preceding output circuit and each subsequent input select circuit, for receiving an external input variable and the output variable output from each preceding output circuit, and for selectively distributing all or part of an external output variable and the input variable based on connection information.

A new reconfigurable cascadable all-optical on-chip device is presented. The gate operates by combining the Vernier effect with a novel effect, the gain-index lever, to help shift the dominant lasing mode from a mode where the laser light is output at one facet to a mode where it is output at the other facet. Since the laser remains above threshold, the speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal optical modulation speed of the laser, which can be on the order of up to about tens of GHz. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog optical or electrical signal at the gate selection port. Other all-optical functionality includes wavelength conversion, signal duplication, threshold switching, analog to digital conversion, digital to analog conversion, signal routing, and environment sensing. Since each gate can perform different operations, the functionality of such a cascaded circuit grows exponentially.