High-speed master-slave type D trigger in low power consumption

Abstract

D trigger is composed of driving and triggering two parts of cascaded circuits. The driving circuit includes transmission gate, timeclock controlled inverting circuit and an inverter. Triggering circuit is a difference structure controlled by the timeclock controlled inverting circuits. On/off of transmission gate is controlled by timeclock singnal; when signal is in high, transmission gate is off; and when signal is in low, transmission gate is on. In on state of the transmission gate, input signal in high level is sent to trigger; when next timeclock signal in high level comes, transmission gate is turned to off; and timeclock controlled inverting circuit is turned to on to hold electrical level, and meanwhile trigger is flipped. Advantages are: simple circuit structure, few number of transistor, small area, about 40úÑ less than power consumption of traditional trigger, and about 20úÑ less than delay time. Moreover, difference input in second stage enhances performance for antinoise.

Description

Technical field [0001] The direct application of "high-speed and low-power master-slave D flip-flops" is the design of high-speed and low-power flip-flop circuit units. The proposed circuit is a high-performance D flip-flop circuit unit suitable for high-speed and low-power circuit design. Background technique [0002] With the increasing of the scale and complexity of integrated circuits, the power consumption and heat dissipation of integrated circuits have attracted more and more attention from the industry and academia. Based on the current integrated circuit design style, in large-scale digital circuit systems, the proportion of energy consumed by the clock network to the total energy consumption of the entire circuit has always been high; among them, the power consumption of the clock network is mainly consumed by the clock interconnection line and timing On the circuit unit (flip-flops, registers, etc.), and the power consumption ratio of the two has an increasing trend (s...

AI Technical Summary

Problems solved by technology

The main feature of this circuit structure is that the circuit structure is relatively simple, but because each clock signal inversion will cause the inversion of the internal nodes of the circuit, the power consumption of the circuit is relatively large.

Jiren Yuan proposed a flip-flop structure with improved speed and power consumption (see Jiren Yuan and Christer Svensson, "New Single-Clock CMOS Latches and Flipflops with Improved Speed ​​and Power Savings", IEEE Journal of Solid-State Circuits, Vol. 32, No.1, pp.62-69, Jan 1997), but because there are internal nodes with uncertain potentials in the circuit, unnecessary glitches on internal nodes will be caused, resulting in unnecessary power loss and affecting the stability of the circuit property, making the circuit unit problematic in use

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