Storage device and executive system and method of access operations

Abstract

An embodiment of the invention provides a storage device and an executive system and method of access operations. The device comprises an interlaced busbar, N memory banks and K direct-attached bus banks, wherein the letter K is smaller than or equal to the letter N, the interlaced busbar comprises M main interfaces and S auxiliary interfaces, the letter M is smaller than or equal to the letter S, and each of the M main interfaces is used for receiving continuous address access operations. Each of the N memory banks comprises S memories connected with the S auxiliary interfaces respectively. The interlaced busbar is used for encoding the continuous address access operations to at least one of the N memory banks by means of interlacing. The first one of the K direct-attached bus banks is used for receiving discrete address access operations and connecting the discrete address access operations to at least one of the N memory banks. Through the storage device and the executive system and method of access operations, the efficiency of access operations is guaranteed.

Description

technical field [0001] The present invention relates to the field of electronic technology, and more particularly, to a storage device, a system and a method for performing an access operation. Background technique [0002] Bus design can be divided into interleaved bus design and non-interleaved bus design from the perspective of address decoding. Most of the existing bus designs are based on non-interleaved bus design. In order to allow the software to use storage resources more flexibly, the interleaved bus design is being adopted more and more; the interleaved bus can realize pipeline operation for the large block data access operation sent by each master device, and can fully utilize the bandwidth of the entire system ; But if there is a discrete single operation issued by the master device, the pipeline operation cannot be carried out normally, and the bandwidth utilization rate of the interleaved bus is greatly reduced. In the worst case, the efficiency drops to the o...

AI Technical Summary

Problems solved by technology

In order to allow the software to use storage resources more flexibly, the interleaved bus design is being adopted more and more; the interleaved bus can realize pipeline operation for the large block data access operation sent by each master device, and can fully utilize the bandwidth of the entire system ; But if there is a discrete single operation issued by the master device, the pipeline operation cannot be carried out normally, and the bandwidth utilization rate of the interleaved bus is greatly reduced. In the worst case, the efficiency drops to the original 1 / M (M is the main interface of the bus the number of)

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