An Extended Bit Line Strobe Device

Abstract

The invention provides an extended bit line strobe device, which comprises a plurality of strobe sub-modules, wherein each sub-module comprises eight tube units, two or three strobe tubes in each tube unit are connected to continuous uneven bit lines or continuous even bit lines in continuous bit lines, each bit line is connected to a plurality of strobe tubes in tube units; each strobe sub-module is strobe controlled by an individual twelve control signal applying terminal, each control signal applying terminal can control at least one strobe tube; a plurality of strobe sub-modules reuse four operation signal applying terminal, corresponding tube units of the plurality of strobe sub-modules reuse a same operation signal applying terminal; and two strobe sub-modules are connected through two co-used uneven bit lines and two co-used even bit lines. By adopting the extended bit line strobe device, no more than four strobe control signals can simultaneously strobe any four continuous bit lines from at least 20 continuous bit lines, and thus the randomness and flexibility of the bit line strobe are improved.

Description

technical field

[0001] The invention relates to the field of memory, in particular to an extended bit line gating device of a memory array. Background technique

[0002] As the demand for high-density storage arrays increases, storage arrays with virtual land structures are more and more widely used in storage devices. Virtual land structure storage array see figure 1 , the memory cells cell00, cell01...cellMN of the memory array 10 are arranged into an array in the form of M rows and N columns, each memory cell includes a plurality of connection ports, and one of the connection ports is used as a control port and word line selection The two connection ports are respectively connected to a bit line, and the bit line is connected to the bit line gating device 11, and the bit line connection ports of each column of memory cells share the same bit line with the memory cells of adjacent columns. figure 1 The bit line connection port of the memory cell in the column where the m...

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