Gate driving circuit, array substrate and display device

A technology for gate drive circuits and array substrates, applied in the fields of array substrates, display devices, and gate drive circuits, can solve problems such as short data signal writing time, abnormal screen display, and inability to meet user display effect requirements, and achieve The effect of increasing the writing time and reducing the probability

Active Publication Date: 2016-03-30
HEFEI BOE OPTOELECTRONICS TECH +1
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  • Claims
  • Application Information

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Problems solved by technology

[0005] However, since the resolution of the current liquid crystal display is getting higher and higher, the writing time of the data signal when the gate line signal is output is getting shorter and shorter.
If the gate line drive circuit in the prior art is also used, it is easy to cause abnormal display of the picture due to insufficient writing time of the data signal, so that the high-resolution liquid crystal display is prone to display failure, which cannot meet the user's requirements for display effect. Require

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  • Gate driving circuit, array substrate and display device
  • Gate driving circuit, array substrate and display device
  • Gate driving circuit, array substrate and display device

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Embodiment Construction

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0039] An embodiment of the present invention proposes a gate drive circuit, see figure 1 , the gate drive circuit includes a multi-stage shift register, and each stage of the shift register is connected to the first clock signal line and the second clock signal line.

[0040] Wherein, for any integer N not less than 2, the input end of the Nth s...

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Abstract

The present invention relates to the field of display technology, and specifically provides a gate drive circuit, an array substrate and a display device. On the basis of the prior art, the present invention adds an output switching element controlled by the second clock signal between the input and output of each stage of shift register, and converts the original output of the next stage to The reset connection mode connected to the reset terminal of the upper stage is changed to the reset connection mode in which the output terminal of the N+2th stage is connected to the reset terminal of the Nth stage. Under such a design, the present invention can output the gate line output signal of each shift register in the gate drive circuit in advance, and double its continuous output time, thereby greatly increasing the writing time of the data signal and reducing A small indication of the possibility of malfunction.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a gate drive circuit, an array substrate and a display device. Background technique [0002] Thin film transistor liquid crystal display (TFT-LCD for short) is one of most liquid crystal display screens, which adopts thin film transistor technology, which can significantly improve image quality. [0003] As an important part of the TFT-LCD driver, the main function of the gate drive circuit is to convert the input clock signal through the shift register and add it to the gate line of the liquid crystal display panel. In the multi-stage shift register of the gate driving circuit, each stage is connected to a corresponding gate line to output a gate line driving signal. In the gate drive circuit, the shift registers at all levels are connected to each other, the start signal is input to the first level of each level, and the gate line drive signals are output to the gate ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G09G3/36G09G3/20
CPCG09G3/3677G09G2310/0286G09G2300/0408G11C19/28G09G3/36G09G3/20
Inventor 张晓洁邵贤杰李小和薛伟董职福
Owner HEFEI BOE OPTOELECTRONICS TECH
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