Voltage self-adaptive adjustment circuit and chip

Abstract

The invention discloses a voltage self-adaptive adjustment circuit and a chip. The voltage self-adaptive adjustment circuit comprises a performance classification monitor and a self-adaptive controller, wherein the performance classification monitor is arranged inside the chip and used for detecting the working performance under the current working voltage and outputting a detection result signal to the self-adaptive controller, and the self-adaptive controller is connected with the performance classification monitor and used for outputting a control signal to a power supply management module of the chip according to the detection result signal output by the performance classification monitor, wherein the control signal is used for controlling the chip working voltage regulated by the power supply management module. The voltage self-adaptive adjustment circuit can reduce the test work amount.

Description

technical field [0001] Embodiments of the present invention relate to the field of electronic technology, and more specifically, relate to a voltage self-adaptive adjustment circuit and chip. Background technique [0002] With the development of chip manufacturing technology and the improvement of design integration, the problem of chip power consumption has become an urgent problem to be solved. Technology to reduce chip power consumption In addition to traditional clock gating and other technologies, Adaptive Voltage Scaling (AVS, Adaptive Voltage Scaling) technology has attracted much attention as a new effective and important low power consumption technology. Among them, determining the minimum operating voltage of the chip is the core step of implementing the AVS technology, and the minimum operating voltage must meet the safety requirements of the system under the worst operating conditions. Adding an appropriate voltage margin on the basis of the minimum operating vo...

AI Technical Summary

Problems solved by technology

The above method needs to test a large number of chips, the workload is heavy, and the test process takes a long time

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