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A method and device for supporting low bit rate coding

A low bit rate, coding technology, applied in coding, coding components, error detection coding using multi-bit parity bits, etc., can solve the problems of poor performance of coding and decoding systems, and it is difficult to make full use of coding gain.

Active Publication Date: 2019-11-12
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the current various communication systems use higher code rate LDPC codes to achieve lower code rates through simple rate matching methods, which makes it difficult to fully utilize the coding gain, resulting in poor performance of the encoding and decoding system

Method used

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  • A method and device for supporting low bit rate coding
  • A method and device for supporting low bit rate coding
  • A method and device for supporting low bit rate coding

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0155] The embodiment of the present invention implements a device supporting low bit rate encoding, such as figure 1 As shown, the device at least includes: a repeater 102, an encoder 104, wherein,

[0156] The repeater 102 is configured to repeat i times the source data packet x to be coded k bits, where i is a positive integer;

[0157] The encoder 104 is configured to encode the data packets after the repeater 102, the encoding is LDPC encoding, Turbo encoding or convolutional encoding;

[0158] The repeater 102 is specifically used to directly repeat the source data packet x to be encoded i times; or, the source data packet x includes j sub-data packets, and repeat i times for the j sub-data packets respectively, and j is a positive integer, The value of i can generally be 1 or 2 or 3 or 4 or 5 or 6;

[0159] Specifically, the encoder 104 is an (nb×z, kb×z) LDPC encoder, which encodes a mother code data packet C′, where nb is the number of columns of the basic parity ch...

example 1

[0163] Set the basic parity check matrix Hb 8×16 as follows:

[0164]

[0165] The underlying parity-check matrix Hb shown 8×16 The corresponding code rate is 1 / 2, the expansion factor z=42, the number of matrix rows is 8 rows, and the number of matrix columns is 16 columns. The number shown on the left is the row index, and the number on the top is the column index, and the letter "A" Indicates the systematic bit part matrix, and the letter "B" means the check bit part matrix. The encoder 104 is a (16×42, 8×42) LDPC encoder, and the source data packet to be encoded is a k=80-bit signaling sequence a=[a 0 ,a 1 ,a 2 ,...,a 79 ], when utilizing 1 / 2 code rate LDPC code base parity check matrix to carry out LDPC encoding to signaling sequence a, when obtaining the encoded data packet e of n=672 bits, described repeater 102 first repeats signaling sequence a by 1 Times, and extended to get 336-bit data packets d=[d 0 , d 1 ,...,d 335 ], the value of d is as follows:

...

example 2

[0171] Set the basic parity check matrix Hb 8×16 as follows:

[0172]

[0173] The underlying parity-check matrix Hb shown 8×16 The corresponding code rate is 1 / 2, the expansion factor z=42, the number of matrix rows is 8 rows, and the number of matrix columns is 16 columns. The number shown on the left is the row index, and the number on the top is the column index, and the letter "A" Indicates the systematic bit part matrix, and the letter "B" means the check bit part matrix. The encoder 104 is a (16×42, 8×42) LDPC encoder, the basic parity check matrix is ​​an 8×16 matrix, the expansion factor z=42, and the source data to be encoded is grouped into k=40-bit signaling sequence f=[f 0 , f 1 ,..., f 39 ], when using 1 / 2 code rate LDPC code basic parity check matrix to carry out LDPC encoding on the signaling sequence f to obtain n=672-bit encoded data packet h, the repeater 102 first repeats the signaling sequence f by Device 102 repeats 1 time, and expands to obtain ...

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Abstract

The invention discloses a method supporting low code rate encoding, which repeats i times the source data packet to be encoded, and encodes the data packet after i times of repetition; the invention also discloses a method supporting low code rate encoding device.

Description

technical field [0001] The present invention relates to the coding technology of digital communication, in particular to a method and device supporting low code rate coding. Background technique [0002] With the development of wireless digital communication and the emergence of various high-speed and bursty services, people put forward higher and higher requirements for error correction coding technology. Low Density Parity Check Codes (LDPC, Low Density Parity CheckCodes) codes are a class of linear block codes that can be defined by a very sparse parity check matrix or a bipartite graph. They were originally discovered by Gallager, so they are called Gora Trellis. After decades of silence, with the development of computer hardware and related theories, MacKay and Neal rediscovered the Gorag code and proved that the Gorag code has the performance close to the Shannon limit. The latest research shows that LDPC codes have the following characteristics: low decoding complex...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11H03M13/15
CPCH03M13/116H03M13/6356H03M13/118H03M13/1137H03M13/114H03M13/1177H03M13/616
Inventor 李立广徐俊袁志锋许进田开波张军王海明何世文
Owner ZTE CORP
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