Construction method for multi-layer-chip efficient X-structure obstacle-avoiding router

An obstacle avoidance router, multi-layer chip technology, applied in instruments, special data processing applications, electrical digital data processing, etc., can solve problems such as difficult problems, achieve compact logic, increase the total length of shared paths, and high efficiency.

Active Publication Date: 2015-12-23
上海立芯软件科技有限公司
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  • Claims
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AI Technical Summary

Problems solved by technology

[0005] The problem is that when considering the three factors of multi-layer chip structure, obstacles, and X-structure at the same time, that is, the structure of the multi-layer obstacle-avoiding X-architecture Steinerminimal tree (ML-OAXSMT) router, the problem will be become very difficult
Because, only a single-layer RSMT router construction has been proved to be an NP-complete problem

Method used

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  • Construction method for multi-layer-chip efficient X-structure obstacle-avoiding router

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Embodiment Construction

[0019] The following combined with the attachment and specific embodiments to further explain the present invention.

[0020] A structural method of high -efficiency X -structctric obstacle -free wiring for multi -layer chips, including the following steps:

[0021] Step S1: According to a set of pin coordinate positions, based on a fast multi-film MST constructing strategy to generate a 3D-OFMST that connects all pins, the 3D-OFMST is the infrastructure of the final ML-OAXSMT;

[0022] Step S2: The XRP information in all edges in 3D-OFMST is calculated and stored these information into two records to generate two search tables. These two search tables can provide information support for the follow-up operation of the wiring;

[0023] Step S3: Based on a quick check table, by converting each edge of 3D-OFMST into a XRP to generate a ML-XSST, and the ML-XSST will be converted into a ML-OAXST;

[0024] Step S4: Further optimize the two perspectives of ML-OAXST, to generate the final...

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Abstract

The invention relates to the technical field of integrated circuit computer-aided design, in particular to a construction method for a multi-layer-chip efficient X-structure obstacle-avoiding router. The method comprises the following steps: step S1, according to a group of given pin coordinate positions, generating a 3D-OFMST (3D Obstacle-free Minimal Spanning Tree) connected with all pins based on a fast multi-fragmentation minimal spanning tree (MST); step S2, calculating XRPs (X Routing Paths) of all edges in the 3D-OFMST, and saving the calculated information to two records to generate two lookup tables; step S3, based on the lookup tables, transforming each edge of the 3D-OFMST to an XRP to generate an ML-XST (Multi-layer X-architecture Steiner Tree), and transforming the ML-XSTs to an ML-OAXST (Multi-layer Obstacle-avoiding X-architecture Steiner Tree); step S4, further optimizing the ML-OAXST from global and local perspectives so as to generate a final ML-OAXSMT.

Description

Technical field [0001] The present invention is an integrated circuit computer -assisted design technology field, which involves a problem of high -efficiency X structured barrier wiring structures for multi -layer chips. Background technique [0002] Stana's smallest tree is one of the most important mathematical models in the field of map theory, and has been widely used to many research fields.Especially in 1966, the right -angle structure proposed by Hanna (RSMT) has been widely applied to multiple stages designed by the design of modern oversized integrated circuits (VLSI).For example, in the early design stage, including division, cloth planning and layout, RSMT can be used to effectively estimate many performance indicators of chips, such as line length, congestion, and extension.During the overall wiring and detailed wiring phase, RSMT can be used to construct the final connection topology of each line network.In addition, with the sharp increase in the density of modern ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 郭文忠黄兴刘耿耿陈国龙
Owner 上海立芯软件科技有限公司
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