Voltage regulation circuit, output regulating voltage generation method thereof and integrated circuit

Abstract

The invention provides a voltage regulation circuit, an output regulating voltage generation method thereof and an integrated circuit. According to the method, a regulating driving tube circuit and an output regulating voltage correcting circuit are included, the regulating driving tube circuit comprises a plurality of driving units and a sampling point, the driving units output regulating voltage, the sampling point samples the output regulating voltage of the driving units, the output regulating voltage correcting circuit is connected with the sampling point and samples the output regulating voltage of at least two driving units through the sampling point, and feedback voltage is generated according to the at least two output regulating voltage obtained through sampling and output to a target circuit through the resistance feedback network proportion. According to the voltage regulation circuit, the output regulating voltage generation method thereof and the integrated circuit, after LDO output regulating values are arranged and corrected, the output voltage value is closer to an actually-needed output voltage value on average statistically, and the technical problem that the output average voltage at the node of a unit, connected with an SRAM Memory cell, of an existing LDO is greatly different from the target output regulating voltage is solved.

Description

technical field [0001] The invention relates to the field of field programmable array devices, in particular to an LDO (low-drop output, voltage regulating circuit) and a method for generating an output regulating voltage thereof, and an integrated circuit. Background technique [0002] SRAM (Static Random Access Memory) is a type of RAM (Random Access Memory), which is mainly used to configure the data bits of the storage unit, and is used a lot in consumer electronics; the storage unit (memorycell) in the SRAM circuit is distributed in an array, with Independent address lines and data lines; with the further reduction of process size, the density of SRAM cells is getting higher and higher, and the power supply of SRAM cells is becoming more and more sensitive; the power supply change of SRAM cells directly affects the timing of subsequent modules of SRAM cells The required margin. Therefore, in SRAMLDO design, an LDO that varies relatively little with PVT (process, power ...

AI Technical Summary

Problems solved by technology

[0003] Currently in the SRAMLDO design, the SRAMLDO architecture mainly includes two parts: the operational amplifier circuit and the regulator driving MOSFET circuit; due to the large number of SRAMMemorycell units, SRAMLDO needs to provide a very large Driving to ensure that the SRAMMemorycell units can be driven evenly, and Driverring's layout and wiring and parasitic resistance and capacitance will affect the consistency of the SRAMLDO output voltage adjustment value: the output value difference at the unit node where Driverring is connected to the Memorycell unit is caused by unreasonable layout and layout and layout parasitic resistance, while PVT and device There is a difference between the actual output of SRAMLDO and the ideal LDO output voltage caused by mismatch, which will lead to the deterioration of consistency

[0004] Therefore, those skilled in the art urgently need to provide an LDO to solve the technical problem that the output average voltage at the cell node connected to the SRAMMemorycell and the target output regulation voltage of the existing LDO are too large.

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