Voltage regulation circuit and its output regulation voltage generation method, integrated circuit

Abstract

The invention provides a voltage regulation circuit, an output regulating voltage generation method thereof and an integrated circuit. According to the method, a regulating driving tube circuit and an output regulating voltage correcting circuit are included, the regulating driving tube circuit comprises a plurality of driving units and a sampling point, the driving units output regulating voltage, the sampling point samples the output regulating voltage of the driving units, the output regulating voltage correcting circuit is connected with the sampling point and samples the output regulating voltage of at least two driving units through the sampling point, and feedback voltage is generated according to the at least two output regulating voltage obtained through sampling and output to a target circuit through the resistance feedback network proportion. According to the voltage regulation circuit, the output regulating voltage generation method thereof and the integrated circuit, after LDO output regulating values are arranged and corrected, the output voltage value is closer to an actually-needed output voltage value on average statistically, and the technical problem that the output average voltage at the node of a unit, connected with an SRAM Memory cell, of an existing LDO is greatly different from the target output regulating voltage is solved.

Description

technical field [0001] The invention relates to the field of field programmable array devices, in particular to an LDO (low-drop output, voltage regulating circuit) and a method for generating an output regulating voltage thereof, and an integrated circuit. Background technique [0002] SRAM (Static Random Access Memory) is a type of RAM (Random Access Memory), which is mainly used to configure storage unit data bits, and is widely used in consumer electronics; memory cells in SRAM circuits are distributed in arrays, It has independent address lines and data lines; with the further reduction of process size, the density of SRAM cells is getting higher and higher, and it is more and more sensitive to the power supply of SRAM cells; the change of power supply of SRAM cells directly affects the power of subsequent modules of SRAM cells The margin required by timing. Therefore, in SRAM LDO design, an LDO that varies relatively little with PVT (process, power supply voltage, tem...

AI Technical Summary

Problems solved by technology

[0003] In the current SRAM LDO design, the SRAM LDO architecture mainly includes two parts: the operational amplifier circuit and the regulator drive ring MOSFET circuit; due to the large number of SRAM Memory cells, the SRAM LDO needs to provide a very large Drive ring to Ensure that the SRAM Memory cell unit can be driven evenly, and the layout and wiring of the Driver ring and the parasitic resistance and capacitance will affect the consistency of the SRAM LDO output voltage adjustment value: Driver ring and Memory cell caused by unreasonable layout and wiring and layout parasitic resistance The difference in the output value at the node of the unit connected to the unit, and the difference between the actual output of the SRAM LDO and the ideal LDO output voltage caused by PVT and device mismatch will lead to the deterioration of the consistency

[0004] Therefore, those skilled in the art urgently need to provide an LDO to solve the technical problem that the output average voltage at the cell node where the existing LDO is connected to the SRAM Memory cell is too different from the target output regulation voltage.

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