Alignment method and system of multiple paths of parallel data signals

Abstract

The invention discloses an alignment method and system of multiple paths of parallel data signals, and relates to the field of reception of multiple paths of parallel signals. The method comprises the following steps: performing analog-to-digital conversion on two paths of test analog signals to obtain two paths of test digital signals, computing two paths of adjustment parameters according to the two paths of test digital signals, adjusting the corresponding parallel digital signals according to the adjustment parameters, and the adjusted parallel digital signals are parallel data automatically aligned by the alignment method and system disclosed by the invention. By adoption of the alignment method and system disclosed by the invention, the paths of parallel data can be aligned simply and accurately, receiving terminal data demodulation errors are avoided, use of people is very convenient, and thus the alignment method and system is suitable for popularization.

Description

technical field [0001] The invention relates to the field of receiving multi-channel parallel signals, in particular to a multi-channel parallel data signal alignment method and system. Background technique [0002] In optical communication and wireless communication systems, multiple channels of parallel analog signals, such as the I channel and Q channel of a QPSK (Quadrature Phase Shift Keying, Quadrature Phase Shift Keying) signal, are often received and processed in real time. Multi-channel parallel analog signals are generally converted into multiple parallel digital signals through multiple high-speed ADC (Analog Digital Converter, analog-to-digital converter) chips, and then use high-speed transceiver equipment to receive parallel digital signals and process them. The transceiver device is, for example, an FPGA (Field Programmable Gate Array, Field Programmable Gate Array) and an ASIC (Application Specific Integrated Circuit, Application Specific Integrated Circuit) ...

AI Technical Summary

Problems solved by technology

[0003] However, when going from ADC to FPGA or ASIC, it may be difficult to synchronize the data of each channel due to circuit wiring delay or the internal structure of the high-speed transceiver channel is unstable, and N (N is a positive integer) data is misplaced between each channel of data. Symbol phenomenon, which leads to data demodulation error at the receiving end

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