delay circuit

Abstract

The invention discloses a time-delay circuit comprising a first field effect transistor, a second field effect transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first capacitor. A first terminal of the first field effect transistor is connected with a first terminal of the first resistor and a second terminal of the second resistor; a second terminal of the first field effect transistor is grounded; and a third terminal of the first field effect transistor is connected with a first terminal of the third resistor and a first terminal of the second field effect transistor. A first terminal of the second field effect transistor is connected with a third terminal of the first field effect transistor and a first terminal of the third resistor; a second terminal of the second field effect transistor is grounded; and a third terminal of the second field effect transistor is connected with a first terminal and an output terminal of the fourth resistor. A first terminal of the first resistor is connected with a second terminal of the second resistor and the first terminal of the first field effect transistor and a second terminal of the first resistor is connected with a power supply, a second terminal of the third resistor, and a second terminal of the fourth resistor. And the first capacitor is connected in parallel between the second terminal and the third terminal of the second field effect transistor in parallel. With the time-delay circuit, a technical problem that the delay time of the time-delay circuit can not be adjusted flexibly in the prior art can be solved.

Description

technical field [0001] The invention relates to the field of circuits, in particular to a delay circuit. Background technique [0002] The traditional RC delay circuit is composed of a pull-up resistor R and a pull-down resistor C. However, some chips require a longer delay time. If the value of the resistor R is increased, it may be formed with the pull-down resistor inside the RESET_N pin. Divide the voltage, causing the final RESET voltage to be too low; if the value of capacitor C is increased, the load on VDD will be too large, which may cause abnormal operation of the power supply, especially for dongle applications, whose VDD power comes from other devices, such as desktops, For the DP interface of the notebook, if the capacitance is too large, some computers may not be able to boot. [0003] The traditional RC delay circuit not only cannot achieve a longer delay time, but also cannot flexibly adjust the delay time. [0004] For the above problems, no effective solu...

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present invention provides a delay circuit to at least solve the technical problem that the delay circuit in the prior art cannot flexibly adjust the delay time

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