Embedded type TSV adapter plate structure for numerous-layer wiring

Abstract

The invention relates to an adapter plate structure, in particular to an embedded type TSV adapter plate structure for numerous-layer wiring, which belongs to the technical field of integrated circuit packaging. According to the technical scheme provided by the invention, the embedded type TSV adapter plate structure for numerous-layer wiring comprises an adapter plate body, wherein a wiring adapter plate groove is formed in the adapter plate body in a concave manner, a wiring adapter plate is arranged in the wiring adapter plate groove, numerous-layer wires are arranged on the wiring adapter plate, the wiring adapter plate is electrically connected with an adapter plate upper redistribution layer on the upper surface of the adapter plate body by means of the numerous-layer wires, the adapter plate upper redistribution layer is electrically connected with an adapter plate lower redistribution layer on the lower surface of the adapter plate body by means of filling connectors filled in through vias of the adapter plate body, a plurality of solder balls are arranged on the adapter plate lower redistribution layer, and the solder balls are electrically connected with the adapter plate lower redistribution layer. The embedded type TSV adapter plate structure can effectively increase the number of wiring layers, realizes the high-density chip scale packaging and system packaging, and is safe and reliable.

Description

technical field [0001] The invention relates to an adapter board structure, in particular to an embedded TSV adapter board structure with extremely multi-layer wiring, and belongs to the technical field of integrated circuit packaging. Background technique [0002] With the development of electronic products in the direction of miniaturization, high performance, and high reliability, the degree of system integration is also increasing. In this case, the way to improve performance by further reducing the feature size of integrated circuits and the line width of interconnect lines is limited by the physical properties of materials and equipment technology, and it is difficult for the traditional Moore's Law to continue to develop. [0003] TSV (Through Silicon Via) technology enables vertical interconnection between chips and chips, chips and substrates, effectively shortening the information transmission path, and achieving more functions, higher power, and more terminals in ...

AI Technical Summary

Problems solved by technology

However, the traditional RDL preparation technology is limited by the technological level, and it is very difficult to prepare multi-layer (4 layers and above) rewiring layers, which can no longer meet the development needs of high interconnection density of TSV interposers.

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