Test sensing mapping method for network-on-chip (NoC)

A technology of on-chip network and mapping method, applied in the direction of data exchange network, digital transmission system, electrical components, etc., can solve problems affecting application program execution, increasing test frequency, etc., to improve reliability, reduce system delay, and prevent regional fragmentation effect

Active Publication Date: 2017-11-24
UNIV OF ELECTRONIC SCI & TECH OF CHINA
View PDF5 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] With the rapid development of sub-micron technology, intermittent faults have gradually become one of the limiting factors to achieve high reliability of the network-on-chip (NoC); and the detection of intermittent faults requires increased test frequency, which will affect the application. implement

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Test sensing mapping method for network-on-chip (NoC)
  • Test sensing mapping method for network-on-chip (NoC)
  • Test sensing mapping method for network-on-chip (NoC)

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] The technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0022] Such as figure 1 As shown, a test-aware mapping method for a network-on-chip NoC, including the following steps:

[0023] S1. Determine the mapping head node: determine the mapping head node according to the number of idle adjacent nodes, the number of measurable links and the distance from the control node of each node in the network-on-chip NoC; wherein, the step S1 includes the following sub-steps: S101. According to the number of idle neighbor nodes of each node in the network on chip NoC, screen the nodes of the network on chip NoC; determine whether the screening result is unique, if so, directly use the node as the mapping first node; if not, add the screening result to the preliminary screening node set ; S102. According to ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a test sensing mapping method for a network-on-chip (NoC). The method comprises the following steps that S1, a mapping head node is determined, wherein the mapping head node is determined according to the number of idle neighbor nodes of each node in the NoC, the number of testable links and the distance from a control node; S2, task mapping is carried out, wherein applications of the NoC are regarded as a group of communication tasks, the communication tasks are sequenced according to the communication traffic to form a task queue, and each group of communication tasks of the applications is mapped according to a deterministic mapping strategy from the head node. The test sensing mapping method for the network-on-chip (NoC) is provided, prevents regional fragmentation, reduces the congestion probability, avoids the situation that tests use links occupied by mapping, reduces the system delay and balances the communication distance and the region adjacency degree.

Description

technical field [0001] The present invention relates to a network on chip, in particular to a test perception mapping method for a network on chip NoC. Background technique [0002] The core idea of ​​network-on-chip (NoC) is to introduce computer network technology into chip design, and completely solve the bottleneck problem of on-chip communication from the perspective of architecture. With the advancement of technology and the development of integrated circuit technology, the integration of chips is getting higher and higher, and there are more and more new embedded systems. The original single-core processor can no longer meet the requirements of high-performance and high-frequency embedded systems. requirements; therefore, the multi-core system on a chip has become an ideal choice; the multi-core system on a chip integrates multiple processors or functional modules into one chip, and is widely used because of its advantages in processing performance, power consumption,...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H04L12/733H04L12/727H04L12/721H04L12/933H04L12/26H04L45/122H04L45/121
CPCH04L43/50H04L45/121H04L45/122H04L45/124H04L45/126H04L49/109
Inventor姜书艳武琼陈姝燏黄乐天
OwnerUNIV OF ELECTRONIC SCI & TECH OF CHINA