A test-aware mapping method for network-on-chip NOCs

Abstract

The invention discloses a test-aware mapping method for a network on chip NoC, which includes the following steps: S1. Determine the mapping head node: according to the number of idle adjacent nodes, the number of measurable links and the connection with the control node of each node in the network on chip NoC Determine the distance to map the first node; S2. Perform task mapping: regard the application program of the network-on-chip NoC as a group of communication tasks, sort the communication tasks according to the traffic volume, and form a task queue, starting from the first node, according to deterministic mapping Policies map sets of communication tasks for an application. The present invention provides a test-aware mapping method for network-on-chip (NoC), which prevents regional fragmentation, reduces congestion probability, avoids links occupied by test-use mapping, reduces system delay, and balances communication distance and regional adjacency Spend.

Description

technical field [0001] The present invention relates to a network on chip, in particular to a test perception mapping method for a network on chip NoC. Background technique [0002] The core idea of ​​network-on-chip (NoC) is to introduce computer network technology into chip design, and completely solve the bottleneck problem of on-chip communication from the perspective of architecture. With the advancement of technology and the development of integrated circuit technology, the integration of chips is getting higher and higher, and there are more and more new embedded systems. The original single-core processor can no longer meet the requirements of high-performance and high-frequency embedded systems. requirements; therefore, the multi-core system on a chip has become an ideal choice; the multi-core system on a chip integrates multiple processors or functional modules into one chip, and is widely used because of its advantages in processing performance, power consumption,...

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