A timer simulation verification device and simulation verification method
A technology of simulation verification and timer, applied in the field of integrated circuits, can solve the problems of inability to check the correctness of data and poor real-time performance, and achieve the effect of shortening debugging time and fast positioning
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[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures.
[0036] An embodiment of the present invention provides a simulation verification device for a timer. figure 1 It is a schematic structural diagram of a simulation verification device for a timer provided by an embodiment of the present invention, and the simulation verification device for a timer can be realized by software. Wherein, the timer module can be realized by a hardware description language, such as VHDL language and verilog language. Such as figure 1 As shown, the timer module 10 is used to simulate a...
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