Construction method for single-project and multiple-project compatible wafer diagram

Abstract

The invention provides a construction method for a single-project and multiple-project compatible wafer diagram. The construction method comprises the following steps of acquiring a wafer and attribute information of Die of the wafer, drawing a wafer diagram at an initial state according to the wafer and the attribute information of the Die of the wafer, the wafer at the initial state having a wafer profile and a plurality of dies, acquiring sub-Die attribute information, and drawing the sub-dies according to the sub-Die attribute information and the plurality of die diagrams on the wafer. With addition of die and sub-die type dimensions to a semiconductor wafer diagram, a problem that test of a whole multi-project wafer cannot be completed by a single test can be solved; test on the wholemulti-project wafer can be scanned for once by an external program according to retrieval of type information of the dies and the sub-dies without requirement of multi-stage. With a sub-die integrated layout drawing method in the die, the sub-die can be vividly displayed; and the construction method is easy to use.

Description

technical field [0001] The invention relates to the technical field of wafer map construction methods, in particular to a construction method with single-target and multi-target wafer map. Background technique [0002] In the semiconductor wafer test and measurement process, in order to achieve automated test and measurement, people often use a computer wafer (Wafer) diagram program to record and display the actual semiconductor wafer physical properties, measurement process and measurement results. Generally, the devices (Die) are arranged on the semiconductor according to a certain layout method, and the position, size and dimension of each device, and the direct spacing of the Die are all determined. Specifically, the wafer map mainly plays the following roles in the semiconductor wafer testing process: to describe the shape and physical dimensions of the semiconductor wafer (Wafer) map (diameter, gap or trim size, orientation, etc.); The physical size (length, width, et...

AI Technical Summary

Problems solved by technology

[0009] The object of the present invention is to provide a single-objective and multi-objective wafer map construction method to solve the problem of single wafer map construction method and complex multi-target wafer map construction method in the prior art

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