Self-adaptive digital reset device for phase-locked loop

Abstract

The invention discloses a self-adaptive digital reset device for a phase-locked loop. The reset device comprises a system reset detection logic circuit for detecting whether the system reset is maintained and achieves an expected width through multiple registers; producing valid reset pulse to a mono-stable circuit if the system reset is maintained and achieves the expected width; the mono-stablecircuit for being in a stable state through multiple registers after receiving the valid reset pulse, and then outputting the valid pulse to a power-on delay logic circuit; the power-on delay logic circuit for performing the counting after receiving the valid pulse output by the mono-stable circuit, and maintaining unchanged after achieving a preset threshold value, and outputting trigger pulse toa PLL reset production logic circuit; the PLL reset production logic circuit for producing the reset pulse with required width after receiving the trigger pulse output by the power-on delay logic circuit. The self-adaptive digital reset device disclosed by the invention realizes the reset of the phase-locked loop based on the digital logic, and has the advantages of being capable of realizing theself-adaptive reset, and high in reset efficiency and reliability.

Description

technical field [0001] The present invention relates to the field of phase locked loop (Phase Locked Loop, PLL) technology, in particular to an adaptive digital reset device for a phase locked loop. Background technique [0002] Phase-locked loop PLL is used to generate stable high-frequency clock output, which is the heart of large-scale integrated circuits, especially microprocessors. With the advancement of integrated circuit technology and the increase of the processor's target main frequency, the design of PLL is becoming more and more refined, and stable, reliable and reasonable reset logic has become an indispensable part of the phase-locked loop. The reset signal of the phase-locked loop usually needs to generate a positive pulse with a certain width after the system is powered on and stabilized. At present, this pulse is usually realized by an analog circuit. Width of 1, and then return to zero state. [0003] The phase-locked loop adopts the reset method implemen...

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