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Secure realization device and method for multi-core 8051 processor SOC

An 8051SOC, processor technology, applied in computer security devices, architecture with a single central processing unit, electrical digital data processing, etc., can solve the problems of SPIFLASH data security problems, avoid simple encryption, realize area and function. Low consumption, simple design effect

Active Publication Date: 2018-06-29
BEIJING DWIN TECH
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  • Abstract
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Problems solved by technology

[0007] Although the FLASH chip of the SPI interface is very popular, the data security stored in the SPI FLASH has always been a big problem

Method used

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  • Secure realization device and method for multi-core 8051 processor SOC
  • Secure realization device and method for multi-core 8051 processor SOC
  • Secure realization device and method for multi-core 8051 processor SOC

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Embodiment Construction

[0040] The principles and features of the present invention will be described below with reference to the accompanying drawings. The examples cited are only used to explain the present invention, and are not used to limit the scope of the present invention.

[0041] Such as figure 1 Shown here is a multi-core 8051SOC installation device implementation system of the present invention, including JTAG interface 1, dual-core 8051 SOC CPU0 system 2, dual-core 8051 SOC CPU1 system 3, JTAG CONTROLLER 4, SPIFLASH 5, and security device system 6;

[0042] Such as figure 2 As shown, the security device system is composed of EFUSE electronic fuse 61, MUX digital logic selector 63, JTAG SECURITY 64 and SPI FLASH CONTROLLER 62 control module.

[0043] For JTAG to access external SPIFLASH data, it must first be pre-processed by JTAG CONTROLLER 4. JTAG CONTROLLER analyzes whether the JTAG data is to pass CPU0 system 2 or CPU1 system 3, and concurrent data is sent to the corresponding CPU system, a...

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Abstract

The invention relates to an encryption method and device for data exchange between a multi-core 8051 processor SOC and an off-chip FLASH. A secure realization device system comprises multiple 8051 processors, a JTAG Controller, a Code&Data SRAM and an encryption / decryption processing module; an encryption module comprises an MUX module, an Efuse module, a JTAG security module and a Spi flash controller module; and the processors perform external read-write on an SPI FLASH based on a unique CODE generated by the EFUSE module through the Spi flash controller module; a JTAG interface of the double-core 8051 SOC performs communication with the JTAG security module through the JTAG Controller, the JTAG security module performs encryption / decryption processing through the unique CODE generated by the EFUSE module, and finally data read-write exchange with the SPI FLASH is performed.

Description

Technical field [0001] The invention relates to the field of processor security, in particular to an encryption method and device for data exchange between a multi-core 8051 processor SOC and an off-chip FLASH. Background technique [0002] The 8051 core processor usually does not have on-chip large-capacity data storage space, so it needs an external chip that can store data. One of the low-cost, high-performance chip storage media that is widely used in the modern electronics industry-SPI FLASH is born . However, because the standard SPI FLASH itself does not have the ability to encrypt data, the data security of SPI FLASH has been criticized. [0003] FLASH chip, called "flash memory" in Chinese, is a kind of memory device. The physical characteristics of flash memory are fundamentally different from common memory, that is, all types of DDR, SDRAM, or RDRAM are volatile memory. As long as the current supply is stopped, the data in the memory cannot be retained. Therefore, the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78G06F21/60
CPCG06F15/781G06F21/606
Inventor 王洪刘华平
Owner BEIJING DWIN TECH
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