Electrostatic Discharge Failure Verification Method

Abstract

The invention relates to a verification method for an electrostatic discharge failure. The method comprises the steps that a chip to be verified is subjected to failure analysis, and damage information of the chip to be verified is recorded; damage information of a good-quality chip in the same batch of the chip to be verified is acquired, wherein the damage information of the good-quality chip isobtained after the good-quality chip is subjected to electrostatic discharge simulation damage test analysis; the damage information of the good-quality chip and the damage information of the chip tobe verified are compared and analyzed, and whether or not the electrostatic discharge failure happens to the chip to be verified is judged; when the damage information of the good-quality chip is identical to that of the chip to be verified, it is determined that the electrostatic discharge failure happens to the chip to be verified. According to the verification method for the electrostatic discharge failure, before electrostatic discharge failure analysis, the chip with a suspected electrostatic discharge failure is subjected to electrostatic discharge failure verification, the situation isavoided that an inaccurate result is obtained by directly adopting electrostatic discharge failure analysis, and the reliability of electrostatic discharge failure analysis is improved.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to an electrostatic discharge failure verification method. Background technique [0002] With the development of science and technology, more and more highly integrated and miniaturized integrated circuit chips are used in electronic products. However, due to the continuous reduction of device feature size, continuous thinning of gate oxide layer thickness, and continuous improvement of integration, the failure of integrated circuits has become more serious. ESD (Electrostatic Damage, electrostatic discharge damage) is a typical failure Way. [0003] When leakage is found through the port volt-ampere characteristic test, but the surface of the chip is directly observed to see if there is any obvious burnt after unpacking, the traditional method is to directly treat it as an electrostatic discharge failure for failure analysis. However, the failure caused in this case is not nece...

AI Technical Summary

Problems solved by technology

[0004] Based on this, it is necessary to provide an electrostatic discharge failure verification method for the disadvantages of poor reliability in the traditional electrostatic discharge failure analysis method

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