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A method and device for realizing check node processing

A technology for checking nodes and processing results, which is applied in the direction of error detection coding, coding, and code conversion of multiple parity bits, which can solve the problems of reduced processing performance of check nodes, and achieve performance degradation and improvement Efficiency and the effect of reducing the amount of computation

Active Publication Date: 2022-02-22
UNICORE COMM INC +1
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Problems solved by technology

[0020] On the basis of the extended minimum sum decoding algorithm, the related technology further reduces the amount of calculation through the bubble check algorithm (Bubble check) and the simplified operation bubble detection algorithm; but compared with the extended minimum sum decoding algorithm, the bubble check algorithm and the simplified operation The bubble detection algorithm leads to a decrease in the performance of check node processing; therefore, a method that can not only reduce the calculation amount of check node processing, but also avoid the decline of check node processing performance, so as to further improve the performance of check node processing efficiency

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  • A method and device for realizing check node processing
  • A method and device for realizing check node processing
  • A method and device for realizing check node processing

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[0052] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0053] The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown or described herein.

[0054] figure 1 A flow chart of a method for implementing check node processing in an embodiment of the present invention, such as figure 1 shown, including:

[0055] Step 101: Sort the information elements of each truncated information vector in ascend...

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Abstract

A method and device for realizing check node processing, including: sorting the information elements of each truncated information vector in ascending order according to the confidence value; determining the row and column of the log likelihood ratio according to a preset strategy; According to the log likelihood ratio, the sum of the confidence values ​​corresponding to each symbol value is obtained; the order of the symbol values ​​is determined according to the row and column of the log likelihood ratio, and the bit XOR operation of the symbol values ​​is performed based on the determined symbol value order; according to the log likelihood ratio The sum of the confidence degrees obtained by the comparison operation and the symbol value obtained by the bit XOR operation determine the processing result of the check node. In the embodiment of the present invention, while reducing the calculation amount of check node processing, it avoids the degradation of check node processing performance, and improves the efficiency of check node processing.

Description

technical field [0001] This article relates to but not limited to wireless communication technology, especially a method and device for implementing check node processing. Background technique [0002] Multi-ary low-density parity-check (LDPC) code decoding is applied to wireless communication systems, and the algorithm implementation is complex, including two parts: check node processing and variable node processing; among them, variable node processing is mainly based on channel information and check node The transmitted correction information calculates the confidence of the variable node (the confidence can be measured in the form of probability distribution or log likelihood ratio, both are equivalent); the verification node processing mainly calculates the correction information based on the confidence of the input variable node , the correction information is the confidence level of the sum of the input variables. At present, related technologies mainly study how to ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
CPCH03M13/1105
Inventor 张洪伦钱镱吴红甲王玉宝王志龙高楠马杏叶南腾飞王从瑾张红阳
Owner UNICORE COMM INC
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