A method and device for realizing check node processing
A technology for checking nodes and processing results, which is applied in the direction of error detection coding, coding, and code conversion of multiple parity bits, which can solve the problems of reduced processing performance of check nodes, and achieve performance degradation and improvement Efficiency and the effect of reducing the amount of computation
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[0052] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.
[0053] The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown or described herein.
[0054] figure 1 A flow chart of a method for implementing check node processing in an embodiment of the present invention, such as figure 1 shown, including:
[0055] Step 101: Sort the information elements of each truncated information vector in ascend...
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