Data issuing method and device, equipment and medium

Abstract

The invention provides a data issuing method and device, equipment and a medium. The method comprises the following steps of: constructing a circular queue of a pre-allocated memory for data issuing,dividing the pre-allocated memory into a plurality of fragments so as to correspondingly block and queue the data, and at least comprising the following steps of: obtaining an enqueue interface of thecircular queue; The enqueue thread controling to-be-issued data to enqueue from the enqueue interface through the first virtual processor by using the spin lock; And the dequeuing thread controls data in the circular queue to dequeue through the second virtual processor by utilizing another lock independent of the spin lock to finish data issuing. The embodiment of the invention is applied. Different locks and different virtual processors which are independent of one another can be used for enqueue and dequeue respectively, the enqueue thread and the dequeue thread are decoupled, the queue memory is divided into a plurality of fragments, so that dequeue does not become possible according to the enqueue size, dequeue data is convenient to parse in a partitioning manner, and the improvementis beneficial to improving the reliability and efficiency of configuration data issuing.

Description

technical field [0001] The present application relates to the technical field of computer networks, and in particular to a method, device, device, and medium for delivering data. Background technique [0002] With the development of network technology, high concurrency, high throughput, and low latency have become important indicators of network equipment performance. Field-programmable gate array (Field-Programmable Gate Array, FPGA) Unit, CPU), processing packets is relatively efficient, but it is short in processing complicated and complex configurations of devices. [0003] At present, in order to give full play to the respective advantages of FPGA and CPU, the "FPGA+CPU" solution can be adopted in terms of hardware architecture. On the one hand, the characteristics of FPGA can be used to improve product performance, and on the other hand, the characteristics of CPU can be used to process and store various configuration data. , and then directly call the driver interfac...

AI Technical Summary

Problems solved by technology

[0002] With the development of network technology, high concurrency, high throughput, and low latency have become important indicators of network equipment performance. Field-programmable gate array (Field-Programmable Gate Array, FPGA) Unit, CPU), the processing of messages is relatively efficient, but there is a shortage in dealing with cumbersome and complex configurations of devices

[0003] At present, in order to give full play to the respective advantages of FPGA and CPU, the "FPGA+CPU" solution can be adopted in terms of hardware architecture. On the one hand, the characteristics of FPGA can be used to improve product performance, and on the other hand, the characteristics of CPU can be used to process and store various configuration data. , and then directly call the driver interface, and send the configuration data to the FPGA through the Peripheral Component Interconnect Express (PCIE) channel. However, when the amount of configuration data is large, the FPGA may not be able to receive it in time, so there is a risk of configuration data loss , and the delivery efficiency is also low

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