A data delivery method, device, equipment, and medium

Abstract

The present application provides a data delivery method, device, equipment, and medium. Construct a circular queue with pre-allocated memory for data delivery. The pre-allocated memory is divided into multiple fragments so that the data can be enqueued in blocks accordingly. The method at least includes: obtaining the enqueuing interface of the circular queue; The thread uses the spin lock to control the data to be sent to enter the queue through the enqueue interface through the first virtual processor; the dequeuing thread uses another lock independent of the spin lock to control the data in the circular queue through the second virtual processor. The data is dequeued and the data distribution is completed. Applying the embodiment of the present application, different locks and different virtual processors that are independent of each other can be used for enqueue and dequeue respectively, the enqueue thread and the dequeue thread are decoupled, and the queue memory is divided into multiple fragments so that the queue memory is not read out according to the enqueue size. The team is possible, and the data out of the team can be easily analyzed in blocks. These improvements help to improve the reliability and efficiency of configuration data delivery.

Description

technical field [0001] The present application relates to the technical field of computer networks, and in particular to a method, device, device, and medium for delivering data. Background technique [0002] With the development of network technology, high concurrency, high throughput, and low latency have become important indicators of network equipment performance. Field-programmable gate array (Field-Programmable Gate Array, FPGA) Unit, CPU), processing packets is relatively efficient, but it is short in dealing with complicated and complex configurations of devices. [0003] At present, in order to give full play to the respective advantages of FPGA and CPU, the "FPGA+CPU" solution can be adopted in terms of hardware architecture. On the one hand, the characteristics of FPGA can be used to improve product performance, and on the other hand, the characteristics of CPU can be used to process and store various configuration data. , and then directly call the driver interf...

AI Technical Summary

Problems solved by technology

[0002] With the development of network technology, high concurrency, high throughput, and low latency have become important indicators of network equipment performance. Field-programmable gate array (Field-Programmable Gate Array, FPGA) Unit, CPU), the processing of messages is relatively efficient, but it is short in dealing with cumbersome and complex configurations of devices

[0003] At present, in order to give full play to the respective advantages of FPGA and CPU, the "FPGA+CPU" solution can be adopted in terms of hardware architecture. On the one hand, the characteristics of FPGA can be used to improve product performance, and on the other hand, the characteristics of CPU can be used to process and store various configuration data. , and then directly call the driver interface, and send the configuration data to the FPGA through the Peripheral Component Interconnect Express (PCIE) channel. However, when the amount of configuration data is large, the FPGA may not be able to receive it in time, so there is a risk of configuration data loss , and the delivery efficiency is also low

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