Tag storage bit readout comparison circuit and tag data readout comparison circuit

A comparison circuit and tag storage technology, which is applied in the circuit field, can solve the problems that the speed of the tag storage bit readout comparison circuit needs to be improved, and achieve the effects of improving the readout and comparison speed, reducing error interference, and improving accuracy

Active Publication Date: 2020-10-13
CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The speed of the existing label storage bit read comparison circuit needs to be improved

Method used

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  • Tag storage bit readout comparison circuit and tag data readout comparison circuit
  • Tag storage bit readout comparison circuit and tag data readout comparison circuit
  • Tag storage bit readout comparison circuit and tag data readout comparison circuit

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Experimental program
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Embodiment Construction

[0039] As described in the background art, the readout and comparison speed of the existing tag memory needs to be improved.

[0040] figure 1 It is a schematic diagram of the structure of a tag storage bit readout comparison circuit. In the reading and comparison of the data of the tag storage bit, it is first necessary to read the tag data from the Static Random-Access Memory (SRAM) 11, and the address bit signal obtained by reading the tag data passes through the bit line The sensitive amplifier 12 is connected, and the address bit amplified signal outputted by the sensitive amplifier 12 is latched by the latch 13. The address bit amplifying signal DOUT output by the latch 13 is connected to the comparator 14 and compared with the target address bit signal Tagin of the externally connected target tag data. The comparator 14 compares the address bit amplifying signal DOUT and the target address bit signal Tagin The comparison result signal Hit is output.

[0041] Among them, th...

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PUM

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Abstract

The embodiment of the invention discloses a tag storage bit reading comparison circuit and a tag data reading comparison circuit. The tag storage bit reading comparison circuit comprises an address bit data reading circuit, a target address bit signal input circuit connected with the address bit data reading circuit, and a bit comparison circuit connected with the address bit data reading circuitand the target address bit signal input circuit respectively. According to the technical scheme provided by the embodiment of the invention, the data reading and comparing speed of the tag memory canbe improved.

Description

Technical field [0001] The invention relates to the field of circuits, in particular to a tag storage bit readout comparison circuit and a tag data readout comparison circuit. Background technique [0002] Tagarray (tag memory array) is used to store the tag value corresponding to the cache data. The tag value includes the high-order address data of the CPU and the corresponding flag information. The address data includes multiple address bits. According to the data organization of the cache, there are full associative, group associative, and direct mapping methods, and various methods correspond to different tag memories. When the CPU is running, when the cache data needs to be accessed, the logical address sent by the CPU to access the cache data is first compared with the content of the tag address memory, and the cache data is accessed when it hits. [0003] In the CPU, the speed of accessing the cache is very important, which is directly related to the performance of the CPU'...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/419G11C11/418G11C7/22
Inventor 杨昌楷黄瑞锋王建龙
Owner CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO LTD
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