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Parallel access device and method and chip

A technology of access device and access method, which is applied in the direction of machine execution device, concurrent instruction execution, program control design, etc., can solve the problems of long data access time, low efficiency of data access operation, and high power consumption of related hardware. Achieve the effects of avoiding lane access conflicts, shortening overall time consumption, and reducing power consumption

Active Publication Date: 2020-05-15
中昊芯英(杭州)科技有限公司
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  • Application Information

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Problems solved by technology

[0004] In view of this, the present invention provides a parallel access device, method, and chip to solve the problem of low efficiency of data access operations, high power consumption of related hardware, and data storage problems caused by access conflicts caused by conflict detection in integrated circuits. The problem of taking a long time

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  • Parallel access device and method and chip
  • Parallel access device and method and chip
  • Parallel access device and method and chip

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Embodiment Construction

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0045] It should be noted that when an element is said to be "connected" to another element, or to say that an element is "connected" or "connected" to another or more elements, it may be directly connected to another element or indirectly connected to the other element.

[0046] Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of ...

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Abstract

The embodiment of the invention discloses a parallel access method, a parallel access device and a chip, which can be used for realizing parallel storage or reading operation of data in the technicalfield of integrated circuits. A target address is generated for a plurality of lanes through an address generator. Lanes access corresponding storage positions in an RAM according to a target address,and data access operation is carried out in parallel. According to the invention, the address generator generates the target address for the lanes. The lane step length generation unit is used for generating the lane step length, the lane step length is K times of the step length, and the generated lane step lengths are different under the control of the same SIMD control instruction, so that thetarget address generated by the address generation unit is ensured not to form an access conflict. Therefore, the power consumption of related hardware can be reduced on the premise of ensuring laneparallel conflict-free access to the memory, and meanwhile, the overall time consumption of data parallel access operation is also shortened.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a parallel access device and method as well as a chip. Background technique [0002] With the development of science and technology and the progress of society, integrated circuit design has been widely used, and more and more electronic devices have entered people's daily life, which not only brings convenience to people's daily life, but also further promotes the development of science and technology. Innovation and R&D. In the field of integrated circuit design, data access is one of the very important technologies. The processor accesses the data through the load (load) instruction and the storage (store) instruction to access the memory. When the processor needs to use the data in the memory, it uses the load instruction to load the data at the corresponding address in the memory to the corresponding register. In , when the processor needs to store data, the st...

Claims

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Application Information

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IPC IPC(8): G06F9/38
CPCG06F9/3887
Inventor 杨龚轶凡郑瀚寻闯小明周远航
Owner 中昊芯英(杭州)科技有限公司
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