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An acquisition method and address technology, applied in the field of linear address acquisition methods and devices, capable of solving problems such as addressing errors
Inactive Publication Date: 2020-07-03
GIGADEVICE SEMICON (BEIJING) INC
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[0004] However, the inventor found in the process of studying the above-mentioned technical solution that the above-mentioned technical solution has the following defects: NandFlash is also divided into MLC NandFlash (Multi Level Cell, multi-level cell flash memory), TLC NandFlash (Triple Level Cell, three-layer cell flash memory) ), etc.; for MLCNandFlash, the number of Pages contained in each WL is an integer multiple of 2, for TLC NandFlash, the number of Pages contained in each WL is an integer multiple of 3, when addressing is performed in units of Pages, addressing often occurs in TLCNandFlash Wrong phenomenon
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Embodiment 1
[0045] refer to figure 1 , which shows a flow chart of a method for obtaining a linear address, which is applied to a non-volatile memory, and may specifically include the following steps:
[0046] Step 101: Receive an addressing instruction, where the addressing instruction includes an address identifier.
[0047]In the embodiment of the present invention, take the address identification as a linear address FWA address identification as an example, FWA is a linear address used by FTL (Flash translation layer, Flash translation layer), and this address includes Die address, Block address, Plane address, WL address . Taking the non-volatile memory as TLC NandFlash as an example, TLC NandFlash can be: there are 2 Dies, one Die has two Planes, one Plane has 2048 Blocks, and one Block has 256 WLs. The composition of FWA can be as follows figure 2 shown.
[0048] In specific applications, such as image 3 As shown, FWA0 can identify the address identifier of the FWA as 0; FWA1...
Embodiment 2
[0091] refer to Figure 4 , which shows a block diagram of a device for acquiring a linear address, which may specifically include:
[0092] A receiving module 410, configured to receive an addressing instruction, wherein the addressing instruction includes an address identifier;
[0093] Die address calculation module 420, for calculating the die address of the wafer corresponding to the addressing instruction according to the address identifier;
[0094] Plane address calculation module 430, for calculating the flash memory chip Plane address corresponding to the addressing instruction according to the address identification;
[0095] Block address calculation module 440, configured to calculate the block address corresponding to the addressing instruction according to the address identifier;
[0096] The WL address calculation module 450 is configured to calculate the word line WL address corresponding to the addressing instruction according to the address identifier;
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Abstract
The embodiment of the invention provides a linear address obtaining method and device, and the method comprises the steps: receiving an addressing instruction which comprises an address identification; calculating a wafer Die address corresponding to the addressing instruction according to the address identifier; according to the address identifier, calculating a flash memorychip Plane address corresponding to the addressing instruction; calculating a block address corresponding to the addressing instruction according to the address identifier; calculating a word line WL address correspondingto the addressing instruction according to the address identifier; and obtaining a target address according to the Die address, the Plane address, the Block address and the WL address. According to the embodiment of the invention, the WL, which is higher than the Page by one level, in the nonvolatile memory is used as the minimum addressing unit, so that the phenomenon that the addressing identifier cannot be aligned with the Page can be avoided, and the addressing accuracy is greatly improved.
Description
technical field [0001] The invention relates to the technical field of memory processing, in particular to a linear address acquisition method and device. Background technique [0002] With the development of various electronic devices and embedded systems, non-volatile memory devices are widely used in electronic products. Take non-volatile memoryNAND flash memory (NAND Flash Memory) as an example. A Nand flash memory is a device. One device can have two chips (Die). One chip can be divided into two flash memory slices (Plane). One flash memory A slice can be divided into 2048 blocks (Block), a block can be divided into 256 pages (Page), and a block can also correspond to 256 WL (Word Line, word line). [0003] In the prior art, the address of the non-volatile memory is usually in the unit of Page, therefore, when addressing the non-volatile memory, the counting unit is also usually in Page. [0004] However, the inventor found in the process of studying the above-mentio...
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