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System on chip performing address translation and method of operating same

A technology of address translation and address, applied in the field of system-on-chip, can solve problems such as system performance degradation

Pending Publication Date: 2022-06-07
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Whenever the MMU receives a translation request for a virtual address, it takes a long latency to receive mapping information from a memory device, and system performance is significantly degraded due to the long latency

Method used

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  • System on chip performing address translation and method of operating same
  • System on chip performing address translation and method of operating same
  • System on chip performing address translation and method of operating same

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Embodiment Construction

[0023] As is conventional in the field of inventive concepts, embodiments are described in terms of functional blocks, units and / or modules and are illustrated in the drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are formed by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques , hard-wired circuits, memory elements, wiring connections, etc.) are physically implemented. Where the blocks, units and / or modules are implemented by a microprocessor or the like, they may be programmed using software (eg, microcode) to perform the various functions discussed herein, and may be implemented by firmware and / or software to drive. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware, or may be implemented as dedicated hardware for performing some fu...

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Abstract

A system on chip that performs address translation and a method of operating the same are provided. The operating method of the system on chip includes outputting a prefetch command in response to an update of mapping information related to a first read target address, the update occurring in a first translation lookaside buffer circuit storing first mapping information of a second address related to a first address; and storing second mapping information of third addresses related to at least some second addresses of an address block in a second translation lookaside buffer circuit in response to the prefetch command, the address block including a second read target address.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2020-0167331 filed in the Korean Intellectual Property Office on December 3, 2020, the disclosure of which is incorporated herein by reference in its entirety. technical field [0002] At least some example embodiments of the inventive concept relate to a system on chip, and more particularly, to a system on chip that performs address translation. Background technique [0003] The memory management unit (MMU) of the system-on-chip receives the mapping information of the physical address related to the virtual address from the memory device in which the address translation table is stored in the process of converting the virtual address to the physical address. Whenever the MMU receives a translation request for a virtual address, it takes a long latency to receive mapping information from the memory device, and system performance is significantly degraded due to the long latency. SUM...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78G06F12/0811
CPCG06F15/7807G06F12/0811G06F12/1027G06F2212/651G06F2212/151G06F2212/1024G06F2212/654G06F12/0864G06F2212/684G06F12/1036G06F2212/681G06F12/0292G06F9/3802G06F12/0862G06F2212/6022G06F2212/68G06F12/10
Inventor 赵成旻金荣奭柳忠桓金宇一
Owner SAMSUNG ELECTRONICS CO LTD
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