Communication system and communication method

A data communication and data technology, applied in the transmission system, time division multiplexing system, multiplexing communication, etc., can solve the problems of receiving end errors, long time intervals, etc., and achieve the effect of reducing the number and clock jitter

Inactive Publication Date: 2004-12-29
ACER INC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the interval of 500 milliseconds is too long for a high-speed communication system, because many clock jitters will be generated in the interval of 500 milliseconds, which will cause errors at the receiving end

Method used

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  • Communication system and communication method
  • Communication system and communication method
  • Communication system and communication method

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Embodiment Construction

[0041] image 3 is a block diagram of a communication system according to the present invention. The communication system 300 includes an E1 asynchronous data link A 302 , a frame switch A 304 , an STM-1 synchronous data channel 306 , a frame switch B 308 and an E1 asynchronous data link B 310 . Wherein the E1 asynchronous data link A 302 includes a first clock reference (not shown) and is basically transmitted at a clock transmission rate of 2.048Mbps±50ppm (ppm means the variation per million pulses); E1 asynchronous Data link B 310 has a second clock reference and basically transmits at a clock transmission rate of 2.048Mbps±50ppm; The clock reference is referenced and basically transmitted at a clock transmission rate of 155.52 Mbps.

[0042] According to the E1 communication protocol, the E1 asynchronous data link may be an actual cable for transmitting data; it may also be a device for processing data. Similarly, according to the STM-1 communication protocol, the STM-...

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Abstract

The present invention is aimed at improving the interface of nonsynchronous data bit stream and synchronous digital series communication system. Said invention provides a full-new data bit format, said data bit format utilizes a low-flutter and low-overhead data frame to ensure the accurate transmission of E1 numeric bit stream on STM-1 nonsynchronous data frequency channel. The compact positive-negative sequence regulation indicator provides a loop filter and VCO combined phase error signal so as to provide accurate clock signal.

Description

technical field [0001] The present invention relates to a synchronous digital serial structure communication system, in particular to a communication system for transmitting a digital bit stream from an asynchronous data channel with a low bit rate to a synchronous data channel with a high bit rate by using data frames with low jitter and low overhead. Background technique [0002] According to the standard of the International Telecommunications Organization (ITU), in a digital bit stream with a transmission rate of 2048Kbps, the maximum capacity is 63 channels. The digital bit stream may be transmitted by an STM-1 data channel with a transmission rate of 155.52 Mbps, and the 2048 Kbps digital bit stream may be asynchronous to the STM-1 data channel. Of the total bandwidth of 155.52 Mbps, only 83 percent of the capacity is used to transmit current signaling data, while the remaining 17 percent of the bandwidth is reserved for overhead data. [0003] The overhead data inclu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/00H04L29/06
Inventor 熊义理
Owner ACER INC
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