Frequency divider with reduced power consumption, apparatus based thereon, and method for high power efficiency frequency divider

Abstract

Apparatus comprising a frequency dividing cell (42) with a prescaler logic, an end-of-cycle logic, a clock input for receiving an input clock (CKin) with frequency fn, a clock output for providing an output clock (CKout) with frequency fm to a subsequent cell (43), a mode control input for receiving a mode control input signal (MDin) from the subsequent cell (43), and a mode control output for providing a mode control output signal (MDout) to a preceding cell (41). The end-of-cycle logic of the frequency dividing cell (42) has a switchable tail current source. This switchable tail current source allows the biasing current of the end-of-cycle logic to be switched off in order to save power.

Description

technical field [0001] The invention relates to a frequency divider, a device and a frequency division method, more specifically, the invention relates to a frequency divider structure, a circuit technology and a method based on a zipper type frequency divider structure. Background technique [0002] In recent years, efforts have been made toward using standard complementary metal-oxide-semiconductor (CMOS) monolithic transceivers in radio frequency (RF) designs. In particular, CMOS implementations of frequency dividers and frequency synthesizers (one of the key building blocks in transceivers) have received a lot of attention. The most noteworthy trends in this regard are chain divider structures and so-called current-switching logic (CML). [0003] Known chain frequency dividers comprise a series of 2 / 3 divider units with identical circuitry. [0004] figure 1 Shown in the traditional 2 / 3 frequency division unit 10, it has five terminals 11-15: clock input terminal (CKi...

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