Dynamic semiconductor memory device
A storage device and semiconductor technology, applied in static memory, information storage, digital memory information and other directions, can solve the problem of poor writing and reading of memory cells, problems with layout area and relief rate of relative column redundant cells, writing and reading Defects and other problems, to achieve the effect of reliable redundancy relief, small layout area, and high redundancy relief rate
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Embodiment 1
[0129] figure 2 It is a configuration diagram showing an example of a shared sense amplifier of the dynamic semiconductor memory device according to the embodiment of the present invention shown in FIG. 1 . exist figure 2 One sense amplifier 6 (60...63, R60, R61) sandwiched by the memory cell board 7 of FIG. 1 is shown in . Such as figure 2 As shown, in this embodiment, the memory cell group N7L on the left and the memory cell group N7R on the right become different column replacement segments.
[0130] figure 2 shown in the composition of this embodiment, and Figure 11 The conventional configuration shown is different in that the two equalization circuits 1L connecting the two pairs of bit line pairs BL0LT, BL0LN and BL1LT, BL1LN of the column redundant memory cell group are connected by group replacement, and the connection is replaced by another group. The two pairs of bit lines BL0RT, BL0RN and BL1RT, BL1RN of the column redundancy memory cell group have a total ...
Embodiment 2
[0139] image 3 It is a figure which shows the more specific structure of one embodiment of this invention. image 3 The constitution of this embodiment shown and figure 2 The above-mentioned embodiment shown is different in that a PMOS transistor whose gate is connected to a constant voltage level V1 is used as the current limiting element 9, and the PMOS transistor is arranged in a strip-shaped layout with a PMOS readout circuit 4 arranged therein. in the N well area.
[0140] As a type of current limiting element, although Figure 10 (A)~ Figure 10 The configuration shown in (D) is disclosed as a prior art, and it is used as a current limiting element from the viewpoint of limiting current characteristics and manufacturing cost Figure 10 (B) PMOS transistor is the best.
[0141] However, in the configuration of the existing current limiting element 9 (refer to Figure 11 ), there is a problem that the layout area is greatly increased due to the creation of new well...
Embodiment 3
[0146] exist image 3 In some cases, the short-circuit defect 15 between the bit line BL0LN and the word line is a short-circuit defect with a certain high resistance. In this case, during the equalization period, the level of the node A0 and the like becomes an intermediate level between the word line standby level (GND, or VKK level) and the bit line precharge power supply VHB. And, the intermediate level is determined by the ratio of the resistance value of the short-circuit defect to the resistance value of the current limiting element 9 and the like. Therefore, the level of the node A0 etc. fluctuates according to various conditions, such as temperature fluctuation. As a result, in the preliminary test in the wafer state, the bit line pair BLOLT, BL0LN, BL1LT, BL1LN, the bit line pair BLORT, BLORN, and the bit line pair BL1RT, BL1RN could not be stably caused to fail to write and read. Case. In this case, in the selection test after the replacement process, a defect oc...
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