Digital signal processing method and apparatus

Abstract

This invented signal process device includes an input data storage logic unit, a FFT / FFT operation logic unit, a FFT factor storage logic unit, multiple and addition operator, overlapping buffer, a parameter and an address controller. The process method includes: setting the number of a circular counter zero, clearing the overlap buffer, selecting the mean length N computed by FFT and an operation length FL, judging number J of the circulation counter and impact response Hi value of each filter, carrying out dot product of FFT factor of impact response Hi and that of the input signals and adding the dot product, adding the results of M dot products in vector to be operated in IFFJ to output part of the values, returning back to the step of judging the count of a circulation counter and impacted response value of each filter.

Description

Digital signal processing method and device technical field The present invention relates to digital signal processing technology, in particular to the digital signal processing technology using filter. Background technique In the prior art, many digital signal processing using causal FIR (Finite Impulse Response) filters will use the following form of convolution and summation operations to obtain the filtering result Y: Y = Σ i = 0 M X i * H i (1) Xi is the i-th input signal, and Hi represents the impulse response of the FIR filter acting on the i-th signal, expressed as: H i , k = 0 , k < 0 h i...

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