Memory cell test circuit for use in semiconductor memory device and its method

Abstract

A memory cell test circuit for use in a semiconductor memory device having a plurality of banks connected to a plurality of global input / output lines, including: a plurality of bank switching units for transferring data outputted from the plurality of banks to the plurality of global input / output lines based on a test mode signal and a plurality of control clock signals; a logic operation unit for performing a logic operation to the data outputted to the plurality of global input / output lines and for outputting a result of the logic operation to a test global input / output line; and a switching unit coupled to the test global input / output line and the plurality of global input / output lines for selectively passing data of the test global input / output line and data of the global input / output lines based on the test mode signal and the plurality of control clock signals.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more particularly, to a circuit for testing memory cells included in the semiconductor memory device. Background technique [0002] Since a semiconductor memory device is highly integrated, the test time taken for testing a memory cell included in the semiconductor memory device is increased. Therefore, recently, a test circuit capable of testing a plurality of memory cells at a time has been developed. That is, the test circuit tests the plurality of memory cells by inputting the same logic data to the plurality of memory cells and detecting output logic values ​​generated by performing a logic operation to output values ​​of the plurality of memory cells. [0003] FIG. 1 is a block diagram for testing a memory cell, which shows a conventional single data rate synchronous semiconductor memory (SDR SDRAM) device. It is assumed here that the traditional SDR SDRAM includes two banks. ...

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Problems solved by technology

[0034] However, as mentioned above, each bank of conventional SDR SDRAM includes test global input / output lines and a logic operation unit, which increases the size of conventional SDR SDRAM

Moreover, if the above-mentioned test circuit is used for a double data rate (DDR) SDRAM or DD2 SDRAM, the size of the test circuit will be further increased

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