51 results about "Bank switching" patented technology

Certain embodiments of the invention may include systems, methods, and apparatus for controlling voltage and reactive power in a distribution network. One method includes estimating at least one present state associated with a distribution network; allocating one or more load zones in the distribution network; predicting load profiles of each zone for a predetermined time period; determining capacitor bank switching schedules for a predetermined time period based at least in part on the at least one present state and the predicted load profiles; and switching capacitor banks according to the capacitor bank switching schedules.

Non-volatile storage devices and methods capable of achieving large capacity solid state drives containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and a memory controller. The bank switching circuitry is integrated onto the memory controller and functionally interposed between the banks of memory devices and the front end of the memory controller. The bank switching circuitry operates to switch accesses by the memory controller among the at least two banks.

A method and apparatus for varactor bank switching for a voltage controlled oscillator is disclosed. Varactor bank switching involves generating a negative bias voltage signal as a control signal for a varactor bank switch in an off-state, the varactor bank switch comprising a pass-gate circuit including switching transistors. Generating the negative bias voltage signal includes employing an active rectifier circuit running at the speed of an oscillation signal, the negative bias voltage signal maintaining the gate-source voltage of the pass-gate circuit below a threshold voltage to prevent said switching transistors from becoming conductive in an off-state.

A two-chip / single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip / single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip / single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies.

A PLL including a VCO with a variable capacitance (such as an LC VCO) including a switched capacitor bank and a varactor, the PLL providing lock range extension over temperature using dynamic capacitor bank switching to dynamically adjust varactor set point based on junction temperature. The varactor is responsive to the Vctrl control voltage to adjust a capacitance of the variable capacitance to control the phase of the PLL signal. Compensation circuitry dynamically adjusts varactor set point by dynamically switching the capacitor bank based in a junction temperature associated with the PLL circuitry, thereby extending PLL lock range over temperature.

An intelligent circuit breaker for shunt capacitor bank switching based on a flexible opening and closing technology, comprising three poles A, B and C and an intelligent controller D. Three-phase power supplies UA, UB and UC are respectively connected with the three poles A, B and C; two ends of a shunt capacitor C1 are respectively connected with the poles A and B; two ends of a shunt capacitor C2 are respectively connected with the poles B and C; two ends of a shunt capacitor C3 are respectively connected with the poles A and C; each of the three poles A, B and C comprises a conductive and arc-extinguishing component (1), a first stroke sensing component (2), a closing damping component (3), a high-voltage insulated component (4), an opening and closing driving component (5), an opening damping component (6), and a second stroke sensing component (7) sequentially connected in series in an axial direction. The intelligent circuit breaker for shunt capacitor bank switching based on the flexible opening and closing technology features a simple structure, reliable operation, convenient maintenance, and a high price-performance ratio; a shunt capacitor bank can be switched frequently; the reactive power compensation equipment for shunt capacitor bank switching achieves effects of reducing loss and saving energy of a power grid, and improving the transmission capacity and electric energy quality of the power grid.

The invention relates to a voltage reactive comprehensive control method for step transformer substations. Time delays are set in main transformer tap adjustment and reactive compensation capacitor switching control of the transformer substations of different voltage levels, wherein different time delays are set in the main transformer tap adjustment and the reactive compensation capacitor switching control of the transformer substations of the last stage and the main transformer tap adjustment and the reactive compensation capacitor switching control of the transformer substations of the next stage to realize time sequence fit of voltage reactive control of the transformer substations of different voltage levels; the same time delay is set in the voltage reactive control of the transformer substations of the same voltage level; and the operation time delay difference of the transformer substations of different voltage levels is at least greater than the required time of the operation. The method can realize reactive voltage optimization control of a global power grid, and can obviously reduce the ubiquitous problems of frequent main transformer tap adjustment and capacitor bank switching oscillation of the current transformer substations.