49 results about "Bank switching" patented technology

Certain embodiments of the invention may include systems, methods, and apparatus for controlling voltage and reactive power in a distribution network. One method includes estimating at least one present state associated with a distribution network; allocating one or more load zones in the distribution network; predicting load profiles of each zone for a predetermined time period; determining capacitor bank switching schedules for a predetermined time period based at least in part on the at least one present state and the predicted load profiles; and switching capacitor banks according to the capacitor bank switching schedules.

Certain embodiments of the invention may include systems, methods, and apparatus for controlling voltage and reactive power in a distribution network. One method includes estimating at least one present state associated with a distribution network; allocating one or more load zones in the distribution network; predicting load profiles of each zone for a predetermined time period; determining capacitor bank switching schedules for a predetermined time period based at least in part on the at least one present state and the predicted load profiles; and switching capacitor banks according to the capacitor bank switching schedules.

A semiconductor memory device is of a bank switching type having a plurality of memory array banks provided in a memory chip which can be switched from one to another for storage operation. The semiconductor memory device includes: a plurality of memory arrays in the memory array banks; an input / output circuit for transmitting information data between the memory arrays and the outside; a data bus for connecting between the memory arrays and the input / output circuit; and N-channel transistors provided across the data bus. The data bus consists of a plurality of adjacent lines. Each of N-channel transistors is connected at their drain to the corresponding lines of the data bus while at their source to the ground. When a multi-bit test is commenced for writing and reading data on the memory arrays, the N-channel transistors are turned on to connect the lines of the data bus to the ground.

The invention relates to a contact with a fixed fracture and having short-circuit current breaking capability and a vacuum arc extinguishing chamber. The contact comprises a group of fixed fracture contact and a group of movable fracture contact, wherein the movable fracture contact is arranged inside the fixed fracture contact when being in a switching-off state. The vacuum arc extinguishing chamber comprises the contact, a shell and a shielding cover, and the contact is provided with the fixed fracture and has short-circuit current breaking capability. By the contact and the vacuum arc extinguishing chamber, the problems of structure complexity of a traditional composite magnetic field contact structure and other vacuum arc extinguishing chambers with regard to capacity current breaking design are solved, deficiency of magnetic field control on vacuum arc and the like are solved; the electric field shielding and protection of the fixed fracture contact on the movable fracture contact are achieved, and the influence of defects formed on the surface of the movable fracture contact on breakdown during the capacitive closing process is avoided; the breaking function and the insulation function are separated, the breaking function is achieved by the composite magnetic field contact, the insulation function is achieved by the fixed contact, and the contact can be used for breaking short-circuit current and also can be used for switching capacitive current such as reactive compensation field of capacitor bank switching and the like.

Non-volatile storage devices and methods capable of achieving large capacity solid state drives containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and a memory controller. The bank switching circuitry is integrated onto the memory controller and functionally interposed between the banks of memory devices and the front end of the memory controller. The bank switching circuitry operates to switch accesses by the memory controller among the at least two banks.

A method and apparatus for varactor bank switching for a voltage controlled oscillator is disclosed. Varactor bank switching involves generating a negative bias voltage signal as a control signal for a varactor bank switch in an off-state, the varactor bank switch comprising a pass-gate circuit including switching transistors. Generating the negative bias voltage signal includes employing an active rectifier circuit running at the speed of an oscillation signal, the negative bias voltage signal maintaining the gate-source voltage of the pass-gate circuit below a threshold voltage to prevent said switching transistors from becoming conductive in an off-state.

The invention discloses a capacitor bank switching method under harmonic conditions, and belongs to the technical field of capacitor banks. Harmonic compensation is performed to a maximum extent. The technical scheme includes: firstly, a bus voltage, idle work requirements and harmonic conditions at the position, where compensation is needed, of a transformer substation are determined, and a capacitor bank needing to be compensated is determined through VQC; then an equivalent mathematical model of the transformer substation is given, wherein reactance values of a current limiting reactor and a third winding of a transformer are taken into account; and finally, the harmonic conditions of the transformer substation are summarized to four kinds, a corresponding considering and calculating method is given aiming at each harmonic condition so as to obtain the optimal compensation capacitor bank. The capacitor bank switching method under the harmonic conditions has the advantages that a switching strategy of the capacitor bank in the VQC of the transformer substation under various harmonic conditions, namely, under the various harmonic conditions, capacitor banks with different reactance rates are combined in an optimal mode, and under the premise that the VQC is met, the maximum compensation effects on harmonic waves are achieved.

A two-chip / single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip / single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip / single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies.

A memory cell test circuit for use in a semiconductor memory device having a plurality of banks connected to a plurality of global input / output lines, including: a plurality of bank switching units for transferring data outputted from the plurality of banks to the plurality of global input / output lines based on a test mode signal and a plurality of control clock signals; a logic operation unit for performing a logic operation to the data outputted to the plurality of global input / output lines and for outputting a result of the logic operation to a test global input / output line; and a switching unit coupled to the test global input / output line and the plurality of global input / output lines for selectively passing data of the test global input / output line and data of the global input / output lines based on the test mode signal and the plurality of control clock signals.

The invention discloses a compensating capacitor bank switching method and a compensating capacitor bank switching device adopting the method. The method mainly includes: working out a random function program with output values serving as sequence numbers of compensating capacitor banks, and selecting compensating capacitor banks switched into a power grid and compensating capacitor banks switched out of the power grid according to the random function output values. The compensating capacitor bank switching device comprises a plurality of capacitor banks (6), a capacitor bank switching controller (8), capacitor bank switching control switches (5) and a power factor meter (7), and a microprocessor (15) of the capacitor bank switching controller (8) is connected with a signal output end of the power factor meter (7) through an input interface circuit (13) and is connected with a control signal end of each capacitor bank switching control switch (5) through an output interface circuit (14). Compared with the prior art, the compensating capacitor bank switching method and the compensating capacitor bank switching device are capable of effectively solving the problem of poor operating reliability of a reactive power compensation device.

A PLL including a VCO with a variable capacitance (such as an LC VCO) including a switched capacitor bank and a varactor, the PLL providing lock range extension over temperature using dynamic capacitor bank switching to dynamically adjust varactor set point based on junction temperature. The varactor is responsive to the Vctrl control voltage to adjust a capacitance of the variable capacitance to control the phase of the PLL signal. Compensation circuitry dynamically adjusts varactor set point by dynamically switching the capacitor bank based in a junction temperature associated with the PLL circuitry, thereby extending PLL lock range over temperature.

An intelligent circuit breaker for shunt capacitor bank switching based on a flexible opening and closing technology, comprising three poles A, B and C and an intelligent controller D. Three-phase power supplies UA, UB and UC are respectively connected with the three poles A, B and C; two ends of a shunt capacitor C1 are respectively connected with the poles A and B; two ends of a shunt capacitor C2 are respectively connected with the poles B and C; two ends of a shunt capacitor C3 are respectively connected with the poles A and C; each of the three poles A, B and C comprises a conductive and arc-extinguishing component (1), a first stroke sensing component (2), a closing damping component (3), a high-voltage insulated component (4), an opening and closing driving component (5), an opening damping component (6), and a second stroke sensing component (7) sequentially connected in series in an axial direction. The intelligent circuit breaker for shunt capacitor bank switching based on the flexible opening and closing technology features a simple structure, reliable operation, convenient maintenance, and a high price-performance ratio; a shunt capacitor bank can be switched frequently; the reactive power compensation equipment for shunt capacitor bank switching achieves effects of reducing loss and saving energy of a power grid, and improving the transmission capacity and electric energy quality of the power grid.

The invention relates to a voltage reactive comprehensive control method for step transformer substations. Time delays are set in main transformer tap adjustment and reactive compensation capacitor switching control of the transformer substations of different voltage levels, wherein different time delays are set in the main transformer tap adjustment and the reactive compensation capacitor switching control of the transformer substations of the last stage and the main transformer tap adjustment and the reactive compensation capacitor switching control of the transformer substations of the next stage to realize time sequence fit of voltage reactive control of the transformer substations of different voltage levels; the same time delay is set in the voltage reactive control of the transformer substations of the same voltage level; and the operation time delay difference of the transformer substations of different voltage levels is at least greater than the required time of the operation. The method can realize reactive voltage optimization control of a global power grid, and can obviously reduce the ubiquitous problems of frequent main transformer tap adjustment and capacitor bank switching oscillation of the current transformer substations.

The invention discloses a compensating capacitor bank switching method and a compensating capacitor bank switching device adopting the method. The method mainly includes: working out a random function program with output values serving as sequence numbers of compensating capacitor banks, and selecting compensating capacitor banks switched into a power grid and compensating capacitor banks switched out of the power grid according to the random function output values. The compensating capacitor bank switching device comprises a plurality of capacitor banks (6), a capacitor bank switching controller (8), capacitor bank switching control switches (5) and a power factor meter (7), and a microprocessor (15) of the capacitor bank switching controller (8) is connected with a signal output end of the power factor meter (7) through an input interface circuit (13) and is connected with a control signal end of each capacitor bank switching control switch (5) through an output interface circuit (14). Compared with the prior art, the compensating capacitor bank switching method and the compensating capacitor bank switching device are capable of effectively solving the problem of poor operating reliability of a reactive power compensation device.