43results about How to "Increase lock range" patented technology

A seat track slide device includes a pair of seat tracks. Each of the seat tracks has a lower rail, an upper rail, a lock lever, and a handle. Through manipulation of the handle, each seat track 3 is capable of switching the associated upper rail to a locking state and an unlocking state by selectively engaging and disengaging the lock lever with respect to the lower rail. Each lock lever is inserted into the corresponding upper rail and pivotally supported in the upper rail. An interlock support portion of the lock lever projects into an outer zone with respect to the front end of the upper rail. The interlock support portion of the lock lever supports an interlock support portion of the handle pivotally relative to each other. With the lock lever maintained in the locking state, the handle is allowed to pivot relative to the lock lever in the outer zone with respect to the front end of the upper rail against elastic force produced by a torsion coil spring arranged in the upper rail.

The invention belongs to the technical field of integrated circuits of radiofrequency frequency synthesizers, and particularly relates to a low power consumption injection locked frequency tripler. A circuit comprises a harmonic wave generator and an injection locked oscillator. The harmonic wave generator is formed by a pair of NMOS tubes and is arranged in a weak inversion area in a bias mode, and triple frequency harmonic signals 3f0 with the maximum efficiency are generated by inputting fundamental frequency signals f0. The injection locked oscillator is composed of a pair of cross-coupled transistors, an inductor, a variable capacitor, a digital control capacitor array and an adjustable current source, and the working frequency of the injection locked oscillator is near the 3f0. In a free oscillation mode, the grid electrodes of the NMOS tubes have no input signals, bias currents of the injection locked oscillator are supplied by the adjustable current source, and self-oscillation frequency is output; in an injection locked mode, the grid electrodes of the NMOS tubes have fundamental frequency signals with frequency near the f0, an injection locked frequency tripler circuit is made to be locked at the frequency 3 f0, and the power consumption of the direct currents at the moment is extremely low. The power source voltages of the circuit are 0.8V, and the power consumption of the direct currents is only 0.16mW.

An injection-locked frequency divider for dividing a frequency of an injection signal and obtaining a frequency divided signal is provided. The injection-locked frequency divider includes a signal injection unit and an oscillator. The signal injection unit includes a first input terminal and a second input terminal for receiving the injection signal. The received injection signal exhibits a phase difference of 180° between the first input terminal and the second input terminal. The oscillator includes an inductor unit and a variable capacitance unit. The injection-locked frequency divider is featured with a wide injection locking range, and can be realized with a low operation voltage, and therefore can be conveniently used in different kinds of hybrid ICs.

An injection-locked frequency divider is provided. The injection-locked frequency divider includes a voltage control oscillator (VCO) and a mixer. The VCO includes a LC resonance tank and a negative-resistance generator for generating a differential oscillation signal including a first and a second oscillation signals. The LC resonance tank adjusts a VCO reactance and resonates for generating the differential oscillation signal. The negative-resistance generator coupled to the LC resonance tank eliminates an equivalent resistance generated by the LC resonance tank and maintains the VCO to continuously oscillate. The mixer has a first and a second local input terminals respectively receiving the first and second injected signals included in a differential injected signal, and the first and second radio frequency input terminals respectively receiving the first and second oscillation signals for mixing the differential injected signal with the differential oscillation signal to adjust the output frequency of the differential oscillation signal.

The invention includes a harmonic suppression circuit, an injection-locked frequency divider circuit (ILFD) and associated methods. The harmonic suppression circuit comprises a source voltage, two suppression modules, two input terminals, two smoothed output terminals and a ground. The ILFD comprises a ground, an input transistor, an input terminal, two divider legs, two output terminals and a source voltage. The associated method to improve harmonic suppression comprises acts of synthesizing differential-phase signals and simultaneously suppressing second harmonics of in-phase signals. The method to extent an ILFD's locking range comprises acts of decreasing quality factor while keeping resonance frequency constant.

A clamping device for attaching to an external fixation element of an external fixation system includes first and second jaws each having inner and outer surfaces, with the inner surface of the first jaw and the inner surface of the second jaw together forming a passage configured to receive the external fixation element. A locking system is engageable with the first and the second jaws. A portion of the locking system is moveable relative to the first and the second jaws between a first position where the locking arrangement is configured to prevent release of the external fixation element having a first size from between the first jaw and the second jaw and a second position where the locking arrangement is configured to prevent release of the external fixation element having a second size from between the first jaw and the second jaw.

A phase locked loop circuit and a clock reproduction circuit can operate stably with satisfying both of wide lock range and good jitter characteristics. The phase locked loop circuit for generating a clock signal in synchronized in phase with an input signal, has a phase comparator having an analog characteristics as a phase difference detection output characteristics and detecting a phase difference between the input signal and the clock signal, a first control loop controlled oscillation depending upon the phase difference detection output and a second control loop controlled oscillation depending upon a signal derived from the phase difference detection output with enhancing frequency components near a direct current component and performs low speed control in comparison with the first control loop.

The invention discloses a switchable dual-core injection locking frequency divider with a wide locking range, and the frequency divider enables two self-resonant frequencies to be distributed at different frequencies through employing different parasitic capacitances of a cross coupling tube when two cores are connected and disconnected. The locking ranges in the two modes are added, so the overall locking range is greatly expanded; the resonant cavity oscillates at a lower resonance point of the transformer in two modes, the quality factor of the resonant cavity is optimized to improve the phase noise of the frequency divider, and the better overall performance can be achieved in the aspects of power consumption, output power and the like by optimizing the parameters of the transformer, the injection pipe, the cross coupling pipe and other elements. The structure is simple, and integration is facilitated.

The invention discloses a C-type wingceltis bar and cross beam end adjustable connecting part. The C-type wingceltis bar and cross beam end adjustable connecting part comprises positioning columns andlimiting plates, the four positioning columns are vertically mounted, a C-type wingceltis bar and the end of a cross beam are sequentially stacked up and down, and are interspersed in among the fourpositioning columns in a cross manner, the limiting plates are horizontally mounted, the two ends of the limiting plates are provided with adjusting openings in the length direction, locking blocks sliding in the length direction of the limiting plates are mounted in the adjusting openings, the four limiting plates are mounted on the top ends and the bottom ends of the positioning columns, the four limiting plates are arranged in sequence end to end in a rectangular manner, the adjusting openings in the two ends of the limiting plates are arranged in the ends of the two adjacent positioning columns in a sleeving manner, the locking blocks tightly abut against the positioning columns, and locking assemblies are mounted on the locking blocks. The adjustable connecting part has the advantagesof being suitable for C-type wingceltis bars and cross beams of multiple specification sizes and the large in locking range.

A clamping device includes a body, a clamp arm and a drive mechanism that includes a displacement body displaced linearly, wherein the clamp arm is rotated based on the displacement of the displacement body. The displacement body includes a guide surface for guiding the rotation of the clamp arm, and also for controlling the rotation of the clamp arm while the clamp arm is in a clamping state. The clamping device further includes a push mechanism disposed at a position facing a lever arm and elastically pushing the displacement body toward the lever arm.

The invention provides a phase discriminator circuit of a delay phase-locked loop, which comprises a frequency dividing circuit, a retiming circuit, a reference time delay circuit and a phase discriminator main body circuit. The frequency dividing circuit is connected with the retiming circuit, the retiming circuit is connected with the reference time delay circuit, and the reference time delay circuit is connected with the phase discriminator main body circuit. The phase discrimination circuit of the delay phase-locked loo comprises the frequency division circuit, the retiming circuit, the reference time delay circuit and the phase discriminator main body circuit, wherein the frequency division circuit, the retiming circuit and the reference delay circuit are added on the basis of the phase discriminator main body circuit; thus the delayed frequency division reference clock can be aligned with the frequency division feedback clock, and the locking range of the phase-locked loop is expanded.