A frequency search and error correction method in a clock data recovery circuit

Abstract

A frequency search and error correction method in a clock data recovery circuit, comprising: initializing frequency search algorithm parameters; processing the frequency error characteristic UP / DN signal according to the set algorithm parameters, and starting frequency search, wherein according to the frequency error characteristic UP The / DN signal is counted accordingly. When there is a phase error signal conversion, add 1 to the jump parameter JUMP to obtain the accumulated parameter SUM, and further judge whether to output the frequency search result; set the number of repeated verifications and threshold parameters to obtain the reset The DCRL value verifies the frequency lock result and outputs it. The invention improves the counting accuracy of UP / DN pulses, increases the stability and reliability of frequency locking, prevents false locking in frequency locking and avoids too long frequency locking time, and overcomes the problem of wrong judgment of frequency search caused by random jitter , Accurately complete frequency search and lock, avoiding the problem that CDR cannot work due to wrong frequency lock.

Description

technical field [0001] The invention relates to the field of integrated circuit IC design, in particular to a frequency search and error correction method in a clock data recovery circuit. Background technique [0002] With the explosive growth of data volume in recent years, the transmission, storage and processing of data have raised more and more challenges. The data transmission rate continues to increase, and it has reached hundreds of Gbps at present. The high-speed transmission data inevitably suffers from various interferences and noises in the medium, and the data quality is getting worse and worse, resulting in an increase in the bit error rate, and even the data is completely destroyed. destroy. Therefore, it is necessary to insert a certain amount of clock data recovery circuit in the data transmission path to help save the data from deteriorating to the extent that it cannot be recovered, improve the quality of the data, and facilitate long-distance transmissio...

AI Technical Summary

Problems solved by technology

This scheme overcomes the influence of the data pattern (DataPattern) on the error to a certain extent, but the data jitter (Jitter) will misjudge the statistical results of E / L, thereby further affecting the frequency error, and there are fractional harmonics ( For example, the data rate is equal to two-thirds of the frequency) false locking problem, which causes the frequency error to be too large, and the subsequent phase locking loop cannot converge. Finally, gradually scanning the frequency from the lowest frequency will also reduce the locking speed

[0007] Therefore, in actual implementation and application, (1) there is a problem of too long lock time, which does not meet the requirements for lock time in some standards; (2) when the actual high-speed pseudo-random data (PRBS) signal has jitter input Because of the randomness of the data and the existence of jitter, the frequency will often be falsely locked to other frequency points, and it is observed that the frequency points after each false lock are inconsistent and have a certain degree of randomness, so that the subsequent phase lock (3) At the input rate of fractional harmonics, the system tends to enter false lock, so that the final locked position cannot be reached, resulting in the premature end of the frequency lock process, which cannot be corrected later. Take data sampling

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