Methods and apparatus for decoding ldpc codes

A device and a decoder technology, applied in the direction of code conversion, error correction/detection using block codes, error detection coding using multiple parity bits, etc., can solve problems such as difficulty in message transmission, and achieve overcoming difficulties and effectively The effect of using resources

Inactive Publication Date: 2006-08-30
QUALCOMM INC
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  • Abstract
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Problems solved by technology

[0046] Clearly, the complexity associated with representing LDPC codes for large codewords is frustrating, at least for hardware implementati

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  • Methods and apparatus for decoding ldpc codes
  • Methods and apparatus for decoding ldpc codes
  • Methods and apparatus for decoding ldpc codes

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Embodiment Construction

[0087] As discussed above, the decoding method and apparatus of the present invention will be described in the context of an LDPC decoder embodiment for illustrative purposes. will first refer to Figure 4 and 5 describe the steps involved in the decoding of LDPC codes, followed by a more detailed discussion of various features of the invention.

[0088] Figure 4 An example non-regular LDPC code is shown using a bipartite graph 400 . The graph includes m check nodes 402 , n variable nodes 406 , and multiple edges 404 . Messages between check nodes and mutable nodes are exchanged through edges 404 . Soft input bit y corresponding to received word Y 1 to y n , and the soft (or hard) output x 1 to x n Indicated by reference numeral 408 . Use the label 402' to identify the mth th Check the node, use the label 406' to identify the nth th Variable nodes, while using labels 410, 409 to identify the nth th soft input y n and the nth th soft output x n .

[0089] Variab...

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Abstract

The invention relates to a method for executing parity check information transmission decodes operation, and relative device, wherein said device comprises: one information source for supplying at least one group with Z k-bit information from at least L groups of any Z k-bit information, while Z is positive integer higher than 1, K and L are non-zero positive integer; and node processor which comprises several node processing units, while each unit is used to execute parity check limit node processing operation or/and parity check variable node processing operation, and one switch connecting said information source and the node processing unit. And switch is used to transmit Z k-bit groups between information sources and the node processors, to respond the switch control information to rearrange the information of at least one group.

Description

[0001] This application is a divisional application of the patent application with the application number 02814214.4, the filing date is May 31, 2002, and the title is "Method and Device for Decoding LDPC Codes". [0002] related application [0003] This application claims the benefit of US Provisional Application S.N. 60 / 298,480, filed June 15,2001. technical field [0004] The present invention is directed to methods and devices for detecting and / or correcting errors in binary data, eg by using parity codes, such as Low Density Parity Check (LDPC) codes. Background technique [0005] In the modern information age, binary values, such as ones and zeros, are used to represent and convey various types of information, such as video, audio, statistical information, etc. Unfortunately, during the storage, transfer, and / or processing of binary data, errors may be inadvertently introduced, eg a one may become a zero or vice versa. [0006] Generally, in the case of data transmi...

Claims

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Application Information

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IPC IPC(8): H03M13/11H03M13/00
Inventor 汤姆·理查森瓦拉迪莫·诺维齐科夫
Owner QUALCOMM INC
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