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A forward correcting decoding device and control method

A forward error correction and decoding device technology, which is applied in the field of forward error correction decoding devices and control, can solve the problem that the decoding part cannot realize real-time decoding, and achieve the effect of meeting the requirements of real-time decoding

Inactive Publication Date: 2010-04-07
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0016] The present invention provides a forward error correction decoding device and control method to solve the problem that when the existing forward error correction error control method is actually applied, the decoding part is limited by the bandwidth and cannot realize real-time decoding

Method used

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  • A forward correcting decoding device and control method
  • A forward correcting decoding device and control method
  • A forward correcting decoding device and control method

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Experimental program
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Embodiment 1

[0053] When 16-bit wide downlink frame data realizes real-time FEC decoding, the structure of the decoding device provided by the present invention is as follows: Figure 5 shown, including:

[0054] The first FEC decoding circuit, which includes sequentially connected input buffer module CW_BUF_0, FEC decoding module FEC_CORE_0 and output buffer module FEC_BUF_0;

[0055] The second FEC decoding circuit, which includes sequentially connected input buffer module CW_BUF_1, FEC decoding module FEC_CORE_1 and output buffer module FEC_BUF_1;

[0056] The third FEC decoding circuit, which includes sequentially connected input buffer module CW_BUF_2, FEC decoding module FEC_CORE_2 and output buffer module FEC_BUF_2;

[0057] The frame data segmentation module FEC_IN is connected to the input end of each input buffer module CW_BUF;

[0058] The frame data reassembly module FEC_OUT is connected to the output end of each output buffer module FEC_BUF;

[0059] The first delay module FP...

Embodiment 2

[0090] When the 8-bit wide downlink frame data realizes real-time FEC decoding, the structure of the decoding device provided by the present invention is as follows: Figure 7 shown, including:

[0091] The first FEC decoding circuit, which includes sequentially connected input buffer module CW_BUF_0, FEC decoding module FEC_CORE_0 and output buffer module FEC_BUF_0;

[0092] The second FEC decoding circuit, which includes sequentially connected input buffer module CW_BUF_1, FEC decoding module FEC_CORE_1 and output buffer module FEC_BUF_1;

[0093] The frame data segmentation module FEC_IN is connected to the input end of each input buffer module CW_BUF;

[0094] The frame data reassembly module FEC_OUT is connected to the output end of each output buffer module FEC_BUF;

[0095] The first delay module FP_DELAY is connected between FEC_IN and FEC_OUT;

[0096] The second delay module NUM_RESIDUE_DELAY is connected between CW_BUF_1 and FEC_OUT.

[0097] Similarly, the work...

Embodiment 3

[0103] When 32-bit wide downlink frame data realizes real-time FEC decoding, the structure of the decoding device provided by the present invention is as follows: Figure 9 As shown, a total of five decoding circuits are required to work together, and the decoding device specifically includes:

[0104] The first FEC decoding circuit, which includes sequentially connected input buffer module CW_BUF_0, FEC decoding module FEC_CORE_0 and output buffer module FEC_BUF_0;

[0105] The second FEC decoding circuit, which includes sequentially connected input buffer module CW_BUF_1, FEC decoding module FEC_CORE_1 and output buffer module FEC_BUF_1;

[0106] The third FEC decoding circuit, which includes sequentially connected input buffer module CW_BUF_2, FEC decoding module FEC_CORE_2 and output buffer module FEC_BUF_2;

[0107] A fourth FEC decoding circuit, which includes sequentially connected input buffer module CW_BUF_3, FEC decoding module FEC_CORE_3 and output buffer module FE...

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Abstract

The invention relates to a forward correcting decoder and relative control method, wherein said device comprises forward correct FEC decode circuit, frame data divide module and frame data recombine module; the FEC decode circuit has at least two parallel paths; the frame data divide module receives the frame data transmitted via FEC code method, and divides each frame data via word length sequence; feeds divided data sections into each FEC decode circuit and decodes; the frame data recombine module recombines frame data. The invention can avoid bandwidth limit, in GPON network, to send and decode descending data continuously.

Description

technical field [0001] The invention relates to signal transmission technology, in particular to a forward error correction decoding device and a control method. Background technique [0002] In order to ensure that the signal is transmitted in the channel to avoid the interference of the noise source on the content of the transmitted signal, the communication transmission system usually adopts an error control mechanism. The source and the sink are respectively the sending end and the receiving end of the signal in the communication system. The purpose is to allow the signal to be transmitted from the source to the destination without errors. Such as figure 1 As shown, the source needs to undergo source coding after generating the signal S, and the sink needs to perform source decoding on the signal before receiving the signal. These two are completely reversed processes. The encoding / decoding of the information source mainly completes the encryption of the signal or othe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04B7/005H04L1/00
Inventor 潘文王万万熊焰
Owner HUAWEI TECH CO LTD
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