Deployment of processing elements in non-uniform memory access environments

a technology of non-uniform memory access and processing elements, applied in computing, input/output to record carriers, instruments, etc., can solve the problems of high overhead for maintaining cache coherence across shared memory of different processors, and the synchronization of memory used by processing elements located on a different node of the computer system can be very costly to system performance, so as to reduce memory coherency overhead and increase system efficiency.

Active Publication Date: 2021-01-26
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a way to distribute processing elements in a way that reduces memory coherency issues in a streaming application. This is done by a deployment manager that uses information about the application's operators and the architecture of the nodes to place the processing elements on a single node. This improves efficiency and performance by consolidating threads across nodes and optimizing memory use.

Problems solved by technology

However, maintaining cache coherence across shared memory of different processors requires significant overhead.
Synchronization of memory used by processing elements located on a different node of the computer system can be very costly to system performance.

Method used

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  • Deployment of processing elements in non-uniform memory access environments
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  • Deployment of processing elements in non-uniform memory access environments

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Embodiment Construction

[0015]The disclosure and claims herein relate to a system and method for deploying processing elements of a streaming application in a non-uniform memory access (NUMA) aware manner to reduce memory coherency overhead in a streaming application. The deployment manager is able to utilize information about an application's operators and the architecture of the NUMA nodes to place whole processing elements on a single NUMA node. Where the operators of a processing element would cross NUMA node boundaries, the deployment manager may consolidate the threads of a processing element to place an application's operators on a single NUMA node to increase efficiency of the system.

[0016]Referring to FIG. 1, a computer system 100 is one suitable implementation of a computer system that is capable of performing the computer operations described herein including deploying processing elements of a streaming application in a non-uniform memory access (NUMA) aware manner as described herein. Computer ...

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Abstract

A deployment manager deploys processing elements of a streaming application in a non-uniform memory access (NUMA) aware manner to reduce memory coherency overhead in a streaming application. The deployment manager is able to utilize information about an application's operators and the architecture of the NUMA nodes to place whole processing elements on a single NUMA node. Where the operators of a processing element would cross NUMA node boundaries, the deployment manager may consolidate the threads of a processing element to place an application's operators on a single NUMA node to increase efficiency of the system.

Description

BACKGROUND1. Technical Field[0001]This disclosure generally relates to computer processing, and more specifically relates to a system and method for deploying processing elements in non-uniform memory access environments to reduce cache-coherency issues and improve overall application performance of a streaming application.2. Background Art[0002]Streaming applications are often processed on a computer system with several computers connected in a cluster. Computers in the cluster are often multiprocessor computers with different architectures. Multiprocessor computers often use non-uniform memory access (NUMA) where the memory access time depends on the memory location relative to the processor. These computer systems typically use a small amount of very fast non-shared memory known as cache memory to exploit locality of reference in memory accesses to increase efficiency. However, maintaining cache coherence across shared memory of different processors requires significant overhead....

Claims

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Application Information

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Patent Type & AuthorityPatents(United States)
IPC IPC(8): G06F12/00G06F12/0817G06F3/06
CPCG06F12/0828G06F3/0622G06F3/0655G06F3/0673G06F2212/621G06F9/5038G06F12/0815G06F2209/501G06F2212/1024G06F2212/2542
InventorKOSTER, DAVID M.SANTOSUOSSO, JOHN M.SABOTTA, CHRISTOPHER R.OROZCO, MANUEL
OwnerIBM CORP