NAND memory arrays
a technology of memory arrays and memory arrays, applied in the field of memory devices, can solve problems such as reducing programming speed
Inactive Publication Date: 2007-03-22
MICRON TECH INC
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AI Technical Summary
Benefits of technology
This approach effectively reduces current leakage, preventing inadvertent programming and improving programming speeds by maintaining the performance of drain select gates while enhancing the reliability of memory cells.
Problems solved by technology
However, current leakage (often referred to as gate-induced drain leakage or GIDL) through the drain select gates acts to reduce the increased voltage level of the unselected strings that can cause inadvertent programming of these strings and can reduce programming speeds.
Method used
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[0013] In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The term wafer or substrate used in the following description includes any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as ot...
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A NAND memory array has a plurality of rows of memory cells and a plurality of columns of NAND strings of memory cells. Each NAND string is selectively connected to a bit line through a drain select gate of the respective column. Each of the drain select gates has a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer. Each of the memory cells of each of the NAND strings has a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer. The first dielectric layer is thicker than the second dielectric layer.
Description
RELATED APPLICATION [0001] This application is a divisional application of U.S. application Ser. No. 10 / 920,561, titled “NAND MEMORY ARRAY AND METHODS,” filed Aug. 18, 2004 (pending), which application is commonly assigned and incorporated herein by reference.TECHNICAL FIELD OF THE INVENTION [0002] The present invention relates generally to memory devices and in particular the present invention relates to-NAND memory arrays and methods. BACKGROUND OF THE INVENTION [0003] Memory devices are typically provided as internal storage areas in computers. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address. [0004] One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-e...
Claims
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IPC IPC(8): H01L21/336H01L29/788
CPCG11C16/0483H01L27/115Y10S438/981H01L27/11529H01L27/11526H10B41/41H10B41/40H10B69/00H10B41/35
InventorVIOLETTE, MICHAELDERDERIAN, GAROABBOTT, TODD R.
OwnerMICRON TECH INC