Memory sensing circuit

a memory sensing circuit and memory technology, applied in the field of magnetic memory elements, can solve the problems of data not being accessible, high power dissipation, and access latency

Inactive Publication Date: 2013-05-02
AVALANCHE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The solution enables reliable sensing and writing to MRAM memory cells with reduced switching current and improved thermal stability, enhancing the scalability and cost-effectiveness of magnetic memory technologies.

Problems solved by technology

Though widely used and commonly accepted, such media suffer from a variety of deficiencies, such as access latency, the data not being randomly accessible, higher power dissipation, large physical size and inability to withstand any physical shock.
Other dominant storage devices are dynamic random access memory (DRAM) and static RAM (SRAM) which are volatile and very costly but have fast random read / write access time.
Although NAND-based flash memory is more costly than HDD's, it has replaced magnetic hard drives in many applications such as digital cameras, MP3-players, cell phones, and hand held multimedia devices due, at least in part, to its characteristic of being able to retain data even when power is disconnected.
However, as memory dimension requirements are dictating decreased sizes, scalability is becoming an issue because the designs of NAND-based Flash memory and DRAM memory are becoming difficult to scale with smaller dimensions.
For example, NAND-based flash memory has issues related to capacitive coupling, few electrons / bit, poor error-rate performance and reduced reliability due to decreased read-write endurance.
It is believed that NAND flash, especially multi-bit designs thereof, would be extremely difficult to scale below 45 nanometers.
Likewise, DRAM has issues related to scaling of the trench capacitors leading to very complex designs which are becoming increasingly difficult to manufacture, leading to higher cost.
Design of different memory technology in a product adds to design complexity, time to market and increased costs.
For example, in hand-held multi-media applications incorporating various memory technologies, such as NAND Flash, DRAM and EEPROM / NOR flash memory, complexity of design is increased as are manufacturing costs and time to market.
Another disadvantage is the increase in size of a device that incorporates all of these types of memories therein.
Although these various memory / storage technologies have created many challenges, such as requiring too much current or having a large cell size or not readily scalable, there have been advances made in this field in recent years.
If the magnetic orientations of the two magnetic layers are parallel, electrons have a relatively easy time tunneling through the tunneling layer, otherwise, tunneling is difficult and some of the electrons are reflected at the interface.
However, one of the problems associated with the foregoing is that the value of the V0 can not be lowered indefinitely because of the presence of thermal noise as well as noise generated by the switching of signals from one state to another.

Method used

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Embodiment Construction

[0027]In the following description of the embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration of the specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized because structural changes may be made without departing from the scope of the present invention.

[0028]It is understood that as used herein “magnetic memory element”, “memory element”, “reference magnetic memory element” or “reference memory element”, or “magnetic random access memory (MRAM)” all refer to magnetic memory that is made of MTJ. Various embodiments of the structure used for a memory element are shown and discussed in the following documents:[0029]U.S. application Ser. No. 11 / 674,124, filed Feb. 12, 2007, titled “Non-Uniform Switching Based Non-Volatile Magnetic Based Memory” by Ranjan et alia,[0030]U.S. application Ser. No. 11 / 678,515, Filed Feb. 23, 2007, titled “A High C...

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Abstract

A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a divisional application of U.S. patent application Ser. No. 12 / 125,866, filed on May 22, 2008, by Parviz Keshtbod, and entitled “Memory Sensing Circuit”, which is a continuation-in-part of U.S. application Ser. No. 12 / 040,801 filed on Feb. 29, 2008, entitled “An Improved Low Resistance High-TMR Magnetic Tunnel Junction and Process for Fabrication Thereof,” which is a continuation-in-part of U.S. application Ser. No. 11 / 674,124 filed on Feb. 12, 2007, entitled “Non-Uniform Switching Based Non-Volatile Magnetic Based Memory,” which claims priority to U.S. Provisional Application No. 60 / 853,115 filed on Oct. 20, 2006 entitled “Non-Uniform Switching Based Non-Volatile Magnetic Based Memory”; and is a further continuation-in-part of U.S. application Ser. No. 11 / 678,515 filed Feb. 23, 2007, entitled “A High Capacity Low Cost Multi-State Magnetic Memory,” which claims priority to U.S. Provisional Application No. 60 / 777,012 f...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G11C11/16
CPCG11C11/16G11C11/1659G11C11/1673G11C11/1693
InventorKESHTBOD, PARVIZ
OwnerAVALANCHE TECH