Boundary latch and logic placement to satisfy timing constraints

a logic placement and latch technology, applied in the field of integrated circuit design, can solve the problems of large number of cells, difficult to achieve the effect of physical design without the aid of computers, and complicated connections between cells

Inactive Publication Date: 2015-07-16
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention is a method for designing a circuit layout for an integrated circuit. It involves receiving a description of the circuit design, identifying boundary latches and applying placement constraints, optimizing wirelength while maintaining the constraints, timing requirements, and performing a placement driven by timing requirements. Filtering of ineligible latches takes into account several factors such as (i) whether it is surrounded by a cluster of latches, (ii) its connection to a primary input / output, and (iii) its driving of a certain number of primary outputs. The constraints may include moveboards or region constraints, pre-placement of boundary latches, or applying an attractive force between boundary latches and boundary fixed objects. The technical effects of this invention include improving the performance and efficiency of circuit design, reducing timing delays, and optimizing circuit performance.

Problems solved by technology

An IC may include a very large number of cells and require complicated connections between the cells.
Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers.
However, physical synthesis can take days to complete, and the computational requirements are increasing as designs are ever larger and more gates need to be placed.
There are also more chances for bad placements due to limited area resources and boundary timing constraints (required arrival times or slack) that are applied to the primary inputs or outputs of a circuit or sub-circuit.

Method used

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  • Boundary latch and logic placement to satisfy timing constraints
  • Boundary latch and logic placement to satisfy timing constraints
  • Boundary latch and logic placement to satisfy timing constraints

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[0017]Faster performance and predictability of responses are elements of interest in circuit designs. As process technology scales to the deep and ultra-deep submicron regimes, meeting tight timing constraints is becoming increasingly important to the performance and reliability of IC chips and systems. The issue of design closure with early or incomplete boundary timing constraints is an unsolved problem for current design processes. Designers are generally given difficult boundary timing constraints which drive all of the latches and boundary logic towards the primary inputs (PIs) and primary outputs (POs), causing bad internal latch-to-latch_timing, over buffering, and poor layer assignment. Most of the time, designers are aware that the timing assertions may be bad and will need to be fixed later. Latches are typically placed via traditional wirelength-driven placement, and any problematic latches have to be identified and specifically fixed (re-placement, timing optimization, ...

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Abstract

Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global placement is performed while maintaining the boundary latch placement constraints, and a timing driven placement is performed after implementing timing assertions. Boundary latches are designated using a depth-first search to identify the first latches along interconnection paths with the PI / PO, and filtering out ineligible latches according to designer rules. A latch can be filtered out if it is in a large cluster of latches driven by a primary input or driving a primary output, if it drives too many POs, or is a feed-through latch. Constraints include movebounds, preplacement, or attractive forces between boundary latches and other boundary fixed objects, i.e., a fixed gate or a PI / PO.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention generally relates to integrated circuit design, and more particularly to a method of placing logic in a design as part of a physical synthesis process.[0003]2. Description of the Related Art[0004]Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements combined to perform a logic function. Cell types include, for example, core cells, scan cells, input / output ...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G06F17/50
CPCG06F17/5072G06F2217/06G06F2217/08G06F2217/84G06F30/392G06F2111/06G06F2119/12
InventorALPERT, CHARLES J.AUBEL, MARK D.FORD, GREGORY F.LI, ZHUOSZE, CHIN NGAIVILLARRUBIA, PAUL G.VISWANATHAN, NATARAJAN
OwnerGLOBALFOUNDRIES INC