Source-Side Resource Request Network Admission Control

a network admission control and resource request technology, applied in computing, input/output to record carriers, instruments, etc., can solve the problems of substantially underutilizing the network and available memory bandwidth, conservative injection of memory requests into the network,

Active Publication Date: 2016-12-08
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, typical mechanisms for injecting memory requests into the network tend to be conservative, For example, a node may assume that each memory request will induce a bank conflict and may allocate bandwidth and adjust injection rates accordingly.
Although those mechanisms may maintain quality-of-service constraints, such conservative injection policies may substantially underutilize the network and available memory bandwidth.

Method used

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  • Source-Side Resource Request Network Admission Control
  • Source-Side Resource Request Network Admission Control
  • Source-Side Resource Request Network Admission Control

Examples

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Embodiment Construction

[0005]A method includes adjusting, by a first node, a rate of injection of memory requests by the first node into a network coupled to a memory system. The adjusting is based on an injection policy for the first node and memory request efficiency indicators. The method may include injecting memory requests by the first node into the network coupled to the memory system. The injecting has the rate of injection. The injection policy may be based on an injection rate limit for the first node. The injection policy for the first node may be based on an injection rate limit per memory channel for the first node. The method may include determining the memory request efficiency indicators based on comparisons of target addresses of the memory requests to target addresses of recent memory requests of the first node. The method may include determining the memory request efficiency indicators based on comparisons of corresponding memory request types to request types of recent memory requests ...

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Abstract

A technique for source-side memory request network admission control includes adjusting, by a first node, a rate of injection of memory requests by the first node into a network coupled to a memory system. The adjusting is based on an injection policy for the first node and memory request efficiency indicators. The method may include injecting memory requests by the first node into the network coupled to the memory system. The injecting has the rate of injection. The technique includes adjusting the rate of injection by the first node. The first node adjusts the rate of injection according to an injection policy for the first node and memory request efficiency indicators. The injection policy may be based on an injection rate limit for the first node. The injection policy for the first node may be based on an injection rate limit per memory channel for the first node. The technique may include determining the memory request efficiency indicators based on comparisons of target addresses of the memory requests to addresses of recent memory requests of the first node.

Description

BACKGROUND[0001]Field of the Invention[0002]The present invention is related to computing systems and more particularly to computing systems including multiple requestors for a shared resource.[0003]Description of the Related Art[0004]In general, in computing systems that include multiple nodes (e.g., central processing unit (CPU), processor, graphics processing unit (GPU), coprocessor, Input / Output node, or other node) and a shared resource (e.g., memory system), when sending requests from an individual node to the shared resource, the requests must often be first routed through a network (e.g., a network-on-a-chip (NoC)). Memory requests that target the same page or row of a memory system (e.g., dynamic random access memory (DRAM)) during a period of time may be serviced more efficiently by the memory subsystem due to a reduced number of bank activation and precharge commands needed to service such memory requests, which result in page or row buffer hits, respectively. However, ty...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H04L29/08G06F3/06
CPCH04L67/1097G06F3/067G06F3/0655G06F3/0604
Inventor LOH, GABRIEL H.MORTON, ERIC CHRISTOPHER
Owner ADVANCED MICRO DEVICES INC
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