Virtualization of a reconfigurable data processor
a data processor and virtualization technology, applied in the direction of program control, memory address/allocation/relocation, instruments, etc., can solve the problems of time-consuming and complex procedures for distributing and loading configuration files, and achieve the effect of reducing the time-consuming and labor-intensive execution of procedures
Active Publication Date: 2020-07-09
SAMBANOVA SYST INC
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AI Technical Summary
Benefits of technology
Enables efficient and simultaneous execution of multiple, unrelated application graphs on a single reconfigurable processor by isolating memory access and configuration operations, allowing for dynamic reconfiguration and resource allocation during runtime.
Problems solved by technology
The procedures and supporting structures for distributing and loading configuration files can be complex, and the execution of the procedures can be time consuming.
Method used
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[0042]The following description will typically be with reference to specific structural embodiments and methods. It is to be understood that there is no intention to limit the technology to the specifically disclosed embodiments and methods but that the technology may be practiced using other features, elements, methods and embodiments. Preferred embodiments are described to illustrate the present technology, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows.
[0043]FIG. 1 is a system diagram illustrating a system including a host 120, a memory 140, and a reconfigurable data processor 110. As shown in the example of FIG. 1, the reconfigurable data processor 110 includes an array 190 of configurable units (CUs) and virtualization logic 195. The virtualization logic 195 can include resources that support or enable simultaneous execution of multiple, unrelated applic...
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A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.
Description
BACKGROUNDTechnological Field[0001]The present technology relates to virtualization of reconfigurable architectures, which can be particularly applied to coarse-grain reconfigurable architectures.Description of Related Art[0002]Reconfigurable processors, including field programmable gate arrays (FPGAs), can be configured to implement a variety of functions more efficiently or faster than might be achieved using a general purpose processor executing a computer program. So-called coarse-grain reconfigurable architectures (e.g. CGRAs) are being developed in which the configurable units in the array are more complex than used in typical, more fine-grained FPGAs, and may enable faster or more efficient execution of various classes of functions. For example, CGRAs have been proposed that can enable implementation of energy-efficient accelerators for machine learning and artificial intelligence workloads. See, Prabhakar, et al., “Plasticine: A Reconfigurable Architecture for Parallel Patte...
Claims
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IPC IPC(8): G06F13/40G06F15/78G06F9/455G06F13/16G06F12/10
CPCG06F13/4027G06F12/10G06F15/7839G06F13/1668G06F9/45533G06F2212/657G06F15/7882G06F15/7867Y02D10/00
InventorGROHOSKI, GREGORY FREDERICKJAIRATH, SUMTILUTTRELL, MARKPRABHAKAR, RAGHUSIVARAMAKRISHNAN, RAMSHAH, MANISH K.
OwnerSAMBANOVA SYST INC