Semiconductor memory apparatus and data scrambling method using the same
a memory apparatus and semiconductor technology, applied in the field of not and (nand) type flash memory, can solve the problems of affecting the characteristics of the sense amplifier, adjacent memory cells may be in a capacitive coupling situation, interfere with each other, and the reliability of stored data deterioration, so as to prevent the effect of reducing reliability
Active Publication Date: 2017-05-23
WINBOND ELECTRONICS CORP
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Benefits of technology
This approach enhances the reliability of semiconductor memory devices by enabling suitable scrambling and descrambling during partial page programming, preventing reliability reductions and improving data storage efficiency.
Problems solved by technology
In this kind of flash memory, when programming (write-in) or erasing is repeated, the reliability of the stored data deteriorates.
Due to miniaturization and high integration of memory cells and the distance between memory cells becoming shorter, adjacent memory cells may be in a capacitive coupling situation and interfere with each other.
Furthermore, the uneven distribution of data “0” or data “1” may have an adverse effect on the characteristics of the sense amplifier when data is read-out due to a difference in the floating voltage of the source line voltage.
On the other hand, programming data on the same page n number of times consecutively means that a high programming voltage that will be applied to the page n number of times, so the number of times of programming is limited.
Since the size of the partial data programmed by partial page programming is not fixed but variable, data scrambling can not be properly executed without determining the boundaries of the partial data.
Method used
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[0030]Below, reference will be made to the figures to describe embodiments of the invention in detail. In addition, it should be noted, the figures are not in the same scale with the actual device and each part is illustrated with emphasis for easier understanding.
[0031]FIG. 2 shows a typical structure of a flash memory according to an embodiment of the invention. However, the structure of the flash memory shown here is only an example and the invention is not limited to this type of structure. A flash memory 10 of the embodiment is constructed by including: a memory array 100, with a plurality of memory cells aligned in a matrix shape; an input / output buffer 110 connected to an external input / output terminal I / O and holds input / output data; a scrambling part 120, scrambling data to be programmed to the memory array 100 or descrambling data that is read-out from the memory array 100; a detecting part 130, monitoring data inputted to a page buffer 170 from the external input / output t...
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A semiconductor memory apparatus and a data processing method are provided. The semiconductor memory apparatus gives consideration to partial page programming and data scrambling, and improves the reliability. In the flash memory of the present invention, when data is programmed to a page n times consecutively, identification information and program information are generated. A scrambled data, the location information and the flag information are programmed to a selected page in a memory array. The location information indicates a storage location for a data scrambling in the page selected based on an input address information. The flag information is used to identify a storage region specified by the location information is programmed.
Description
CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Japan application serial no. 2015-065425, filed on Mar. 27, 2015. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.BACKGROUND OF THE INVENTION[0002]Field of the Invention[0003]The invention relates to a Not AND (NAND) type flash memory and such semiconductor memory device, and relates particularly to a data scrambling method of a NAND type flash memory.[0004]Description of Related Art[0005]A NAND type flash storage has a memory array which includes a plurality of blocks, wherein a NAND string constructed by a plurality of storage cells connected in series is formed in one block. Typically, a read-out or programming of data is performed with one page as the unit, and erasing of data is performed with one block as the unit.[0006]Patent document one discloses a data writing method by which reliability of opera...
Claims
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IPC IPC(8): G11C11/34G11C16/26G11C7/10G11C16/34G11C16/04G11C16/10
CPCG11C16/10G11C7/1006G11C16/0483G11C16/26G11C16/3427
InventorSUDO, NAOAKI
OwnerWINBOND ELECTRONICS CORP