Method of making floating-gate memory-cell array with digital logic transistors

Inactive Publication Date: 2007-06-19
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0012]With the control gate and the integrated circuit substrate at 0V, the deep N-well allows application of a positive erasure voltage of perhaps +16V to the source / drain diffusions and the P-well of the nonvolatile memory array during erasure. Alternatively, with the substrate at 0V, a smaller positive erasure voltage (perhaps +12) is applied to the source / drain diffusions and the P-well, and a negative erasure voltage (perhaps −6V) is applied to the control gate. Applications of those voltages permits the cells of the memory array to be erased without the causing field-plate stress at the p-n junctions between the source / drain diffusions and the P-well.

Problems solved by technology

The reverse-bias voltage is the cause of undesirable cell-breakdown-voltage problems during flash erase.
The same cell-breakdown problem occurs if a sufficiently large reverse voltage is applied to the drain diffusion.
In the past, “X-type” cells have been limited to use in ultraviolet-erasable EPROMs.

Method used

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  • Method of making floating-gate memory-cell array with digital logic transistors
  • Method of making floating-gate memory-cell array with digital logic transistors
  • Method of making floating-gate memory-cell array with digital logic transistors

Examples

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Embodiment Construction

[0019]Referring to FIG. 1, a memory device is shown which has an array of rows and columns of memory cells 10, each of which is an insulated gate field effect transistor having a control gate 11, a source 12 and a drain 13. The cells 10 including a floating gate 14 between the control gate 11 and the channel between source 12 and drain 13.

[0020]The control gates 11 of all cells in each row are connected to one of a set of row lines 15. Row lines 15 are connected to an X address decoder 16 which selects one of row lines 15 based on a row address on lines 17. In a read operation, the selected one of the lines 15 goes high, the others remain low.

[0021]The drains 13 of adjacent cells 10 are connected in common to Y output lines 18. The lines 18 are connected through Y output select transistors 19 to a Y output line 20. The gates of the transistors 19 are connected to a Y address decoder 21 via lines 22 which function to apply a supply-level voltage Vcc to one of the lines 22 and hold th...

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Abstract

A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvolatile memory array, deep N-wells are formed for the high-voltage P-channel transistors of the logic circuitry. At the same time the P-well is formed for the nonvolatile memory array, P-wells are formed for the low-voltage N-channel transistors. The memory array contains nonvolatile cells of the type used in the ultra-violet-erasable EPROMs. During erasure, the isolated-well formation allows the source, the drain and the channel of selected cells to be driven to a positive voltage. The isolated well is also driven to a positive voltage equal to, or slightly greater than, the positive voltage applied to the source and drain, thus eliminating the field-plate breakdown-voltage problem.

Description

BACKGROUND OF THE INVENTION[0001]This invention relates to nonvolatile semiconductor memory devices and, more particularly, to flash electrically erasable, programmable, read-only memories (flash EPROMs) having floating-gate-type memory cells and, more particularly to a method of making such devices on a chip while at the same time making digital control circuitry.[0002]An array structure using buried diffusion wells (tanks) is described in U.S. Pat. No. 5,411,908 issued May 2, 1995, and entitled “FLASH EEPROM ARRAY WITH P-TANK INSULATED FROM SUBSTRATE BY DEEP N-TANK”. That patent is assigned to Texas Instruments Incorporated.[0003]The prior-art includes programming and erasing floating-gate memory cells by Fowler-Nordheim tunneling. During flash erasure of floating-gate cells by Fowler-Nordheim tunnelling, the substrate and control gates (wordlines) of each cell are typically connected to 0V, the sources (source lines) of each cell are connected to a positive voltage of perhaps +10...

Claims

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Application Information

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IPC IPC(8): H01L21/8238H01L21/8247H01L27/105
CPCH10B41/49H10B41/40H01L27/105
InventorMAROTTA, GIULIO-GIUSEPPESANTIN, GIOVANNISMAYLING, MICHAEL C.MATSUOKA, MISAKO A.FUKAWA, SATORU
OwnerTEXAS INSTR INC