Method of forming isolation structure of semiconductor device

Abstract

A method for forming an isolation structure of a semiconductor device includes forming an isolation trench on a semiconductor substrate. A first insulating layer is formed over the isolation trench and the substrate. A spin-on-dielectric (SOD) insulating layer is formed over the first insulation layer, the SOD insulating layer filling the isolation trench and extending above an upper level of the isolation trench. The SOD insulating layer provided within the isolation trench is removed to expose an upper portion of the isolation trench, wherein a lower portion of the isolation trench remains filled with the SOD insulating layer. A second insulating layer is formed over the SOD insulating layer that is filling the lower portion of the isolation trench, wherein the second insulating layer fills the upper portion of the isolation trench.

Description

technical field [0001] The present invention relates to a method of forming an isolation structure of a semiconductor device, and more particularly to a method capable of improving the gap fill margin of a trench used for the isolation structure. Background technique [0002] In general, a semiconductor device includes isolation regions for electrically isolating respective circuit patterns. As semiconductor devices become more highly integrated and miniaturized, since the size of an active region and the process margin of a subsequent process depend on an isolation region formed in an initial step, studies for reducing the size of an isolation region have been actively studied. [0003] As semiconductor devices become more highly integrated and miniaturized, the LOCOS isolation method, which has previously been widely used to manufacture semiconductor devices, has largely been eliminated because the LOCOS method requires more space to perform than the Shallow Trench Isolati...

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Problems solved by technology

However, when the aspect ratio of the trench increases due to high integration, it becomes difficult to gap fill the trench with the HDP oxide layer

If the aspect ratio of the trench is higher than 4, it becomes difficult to gap fill the trench with current HDP equipment

In currently developed 60nm NAND flash devices, the aspect ratio of the isolation trenches is about 5.5, which makes it difficult to gap fill the trenches with the HDP oxide layer

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